Datasheet
Table Of Contents
- Figure 1. Block diagram
- 1 Description
- 2 Maximum ratings
- 3 Pin connection
- 4 Electrical characteristics
- 5 Typical electrical performance
- Figure 3. IC consumption vs. VCC
- Figure 4. IC consumption vs. TJ
- Figure 5. VCC Zener voltage vs. TJ
- Figure 6. Startup and UVLO vs. TJ
- Figure 7. Feedback reference vs. TJ
- Figure 8. E/A output clamp levels vs. TJ
- Figure 9. UVLO saturation vs. TJ
- Figure 10. OVP levels vs. TJ
- Figure 11. Inductor saturation threshold vs. TJ
- Figure 12. Vcs clamp vs. TJ
- Figure 13. ZCD sink/source capability vs. TJ
- Figure 14. ZCD clamp level vs. TJ
- Figure 15. R discharge vs. TJ
- Figure 16. Line drop detection threshold vs. TJ
- Figure 17. VMULTpk - VVFF dropout vs. TJ
- Figure 18. PFC_OK threshold vs. TJ
- Figure 19. PFC_OK FFD threshold vs. TJ
- Figure 20. Multiplier characteristics at VFF = 1 V
- Figure 21. Multiplier characteristics at VFF = 3 V
- Figure 22. Multiplier gain vs. TJ
- Figure 23. Gate drive clamp vs. TJ
- Figure 24. Gate drive output saturation vs. TJ
- Figure 25. Delay to output vs. TJ
- Figure 26. Start-up timer period vs. TJ
- 6 Application information
- 7 Application examples and ideas
- Figure 34. Demonstration board EVL6564-100W, wide-range mains: electrical schematic
- Figure 35. L6564 100W TM PFC: compliance to EN61000-3-2 standard
- Figure 36. L6564 100W TM PFC: compliance to JEITA-MITI standard
- Figure 37. L6564 100 W TM PFC: input current waveform at 230 - 50 Hz - 100 W load
- Figure 38. L6564 100W TM PFC: input current waveform at 100 V - 50 Hz - 100 W load
- 8 Package mechanical data
- 9 Order codes
- 10 Revision history
DocID16202 Rev 5 7/33
L6564 Pin connection
33
3 Pin connection
Figure 2. Pin connection
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Table 3. Pin description
N° Name Function
1INV
Inverting input of the error amplifier. The information on the output voltage of the PFC preregulator
is fed into the pin through a resistor divider.
The pin normally features high impedance.
2COMP
Output of the error amplifier. A compensation network is placed between this pin and INV (pin 1) to
achieve stability of the voltage control loop and ensure high power factor and low THD.
To avoid uncontrolled rise of the output voltage at zero load, when the voltage on the pin falls below
2.4 V the gate driver output will be inhibited (burst-mode operation).
3MULT
Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor divider
and provides the sinusoidal reference to the current loop. The voltage on this pin is used also to
derive the information on the RMS mains voltage.
4CS
Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor, the
resulting voltage is applied to this pin and compared with an internal reference to determine
MOSFET’s turn-off.
A second comparison level at 1.7 V detects abnormal currents (e.g. due to boost inductor
saturation) and, on this occurrence, activates a safety procedure that temporarily stops the
converter and limits the stress of the power components.
5V
FF
Second input to the multiplier for 1/V
2
function. A capacitor and a parallel resistor must be
connected from the pin to GND. They complete the internal peak-holding circuit that derives the
information on the RMS mains voltage. The voltage at this pin, a dc level equal to the peak voltage
on pin MULT (3), compensates the control loop gain dependence on the mains voltage. Never
connect the pin directly to GND but with a resistor ranging from 100 K (minimum) to 2 M
(maximum). This pin is internally connected to a comparator in order to provide the brownout (AC
mains undervoltage) protection. A voltage below 0.8 V shuts down (not latched) the IC and brings
its consumption to a considerably lower level. The IC restarts as the voltage at the pin goes above
0.88 V.