Datasheet
Table Of Contents
- Figure 1. Block diagram
- 1 Description
- 2 Maximum ratings
- 3 Pin connection
- 4 Electrical characteristics
- 5 Typical electrical performance
- Figure 3. IC consumption vs. VCC
- Figure 4. IC consumption vs. TJ
- Figure 5. VCC Zener voltage vs. TJ
- Figure 6. Startup and UVLO vs. TJ
- Figure 7. Feedback reference vs. TJ
- Figure 8. E/A output clamp levels vs. TJ
- Figure 9. UVLO saturation vs. TJ
- Figure 10. OVP levels vs. TJ
- Figure 11. Inductor saturation threshold vs. TJ
- Figure 12. Vcs clamp vs. TJ
- Figure 13. ZCD sink/source capability vs. TJ
- Figure 14. ZCD clamp level vs. TJ
- Figure 15. R discharge vs. TJ
- Figure 16. Line drop detection threshold vs. TJ
- Figure 17. VMULTpk - VVFF dropout vs. TJ
- Figure 18. PFC_OK threshold vs. TJ
- Figure 19. PFC_OK FFD threshold vs. TJ
- Figure 20. Multiplier characteristics at VFF = 1 V
- Figure 21. Multiplier characteristics at VFF = 3 V
- Figure 22. Multiplier gain vs. TJ
- Figure 23. Gate drive clamp vs. TJ
- Figure 24. Gate drive output saturation vs. TJ
- Figure 25. Delay to output vs. TJ
- Figure 26. Start-up timer period vs. TJ
- 6 Application information
- 7 Application examples and ideas
- Figure 34. Demonstration board EVL6564-100W, wide-range mains: electrical schematic
- Figure 35. L6564 100W TM PFC: compliance to EN61000-3-2 standard
- Figure 36. L6564 100W TM PFC: compliance to JEITA-MITI standard
- Figure 37. L6564 100 W TM PFC: input current waveform at 230 - 50 Hz - 100 W load
- Figure 38. L6564 100W TM PFC: input current waveform at 100 V - 50 Hz - 100 W load
- 8 Package mechanical data
- 9 Order codes
- 10 Revision history
Application information L6564
20/33 DocID16202 Rev 5
Figure 28. Voltage feed-forward: squarer-divider (1/V
2
) block diagram and transfer characteristic
In this way a change of the line voltage will cause an inversely proportional change of the
half sine amplitude at the output of the multiplier (if the line voltage doubles the amplitude of
the multiplier output will be halved and vice versa) so that the current reference is adapted
to the new operating conditions with (ideally) no need for invoking the slow dynamics of the
error amplifier. Additionally, the loop gain will be constant throughout the input voltage
range, which improves significantly dynamic behavior at low line and simplifies loop design.
Actually, deriving a voltage proportional to the RMS line voltage implies a form of integration,
which has its own time constant. If it is too small the voltage generated will be affected by
a considerable amount of ripple at twice the mains frequency that will cause distortion of the
current reference (resulting in high THD and poor PF); if it is too large there will be
a considerable delay in setting the right amount of feed-forward, resulting in excessive
overshoot and undershoot of the preregulator's output voltage in response to large line
voltage changes. Clearly a trade-off was required.
The L6564 device realizes a NEW voltage feed forward that, with a technique that makes
use of just two external parts, strongly minimizes this time constant trade-off issue
whichever voltage change occurs on the mains, both surges and drops. A capacitor C
FF
and
a resistor RFF, both connected from the pin V
FF
(#5) to ground, complete an internal peak-
holding circuit that provides a DC voltage equal to the peak of the rectified sine wave
applied on pin MULT (#3). In this way, in case of sudden line voltage rise, C
FF
will be rapidly
charged through the low impedance of the internal diode; in case of line voltage drop, an
internal “mains drop” detector enables a low impedance switch which suddenly discharges
C
FF
avoiding long settling time before reaching the new voltage level. The discharge of C
FF
is stopped as its voltage equals the voltage on the pin MULT or if the voltage on the pin V
FF
falls below 0.88 V, to prevent the “Brownout protection” function from being improperly
activated (see Section 6.6: Power management/housekeeping functions on page 25).
As a result of the V
FF
pin functionality, an acceptably low steady-state ripple and low current
distortion can be achieved with a limited undershoot or overshoot on the preregulator's
output.
$0Y
08/7
5HFWLILHGPDLQV
LGHDOGLRGH
FXUUHQW
UHIHUHQFH
9FV[
9
9))
&
))
5
))
($RXWSXW
9
&203
9
08/7,3/,(5
/+
'(7(&725
0$,16'523
9
))
9
08/7
9FV[
9&203 9
$FWXDO
,GHDO
08/7
5HFWLILHGPDLQV
LGHDOGLRGH
FXUUHQW
UHIHUHQFH
9FV[
9
9))
&
))
5
))
($RXWSXW
9
&203
9
08/7,3/,(5
/+
'(7(&725
0$,16'523
08/7
5HFWLILHGPDLQV
LGHDOGLRGH
FXUUHQW
UHIHUHQFH
9FV[
9
9))
&
))
5
))
($RXWSXW
9
&203
9
08/7,3/,(5
/
'(7(&725
0$,16'523
9
))
9
08/7
9FV[
9&203 9
$FWXDO
,GHDO
9
))
9
08/7
9FV[
9&203 9
$FWXDO
,GHDO