Datasheet
Table Of Contents
- Figure 1. Block diagram
- 1 Description
- 2 Maximum ratings
- 3 Pin connection
- 4 Electrical characteristics
- 5 Typical electrical performance
- Figure 3. IC consumption vs. VCC
- Figure 4. IC consumption vs. TJ
- Figure 5. VCC Zener voltage vs. TJ
- Figure 6. Startup and UVLO vs. TJ
- Figure 7. Feedback reference vs. TJ
- Figure 8. E/A output clamp levels vs. TJ
- Figure 9. UVLO saturation vs. TJ
- Figure 10. OVP levels vs. TJ
- Figure 11. Inductor saturation threshold vs. TJ
- Figure 12. Vcs clamp vs. TJ
- Figure 13. ZCD sink/source capability vs. TJ
- Figure 14. ZCD clamp level vs. TJ
- Figure 15. R discharge vs. TJ
- Figure 16. Line drop detection threshold vs. TJ
- Figure 17. VMULTpk - VVFF dropout vs. TJ
- Figure 18. PFC_OK threshold vs. TJ
- Figure 19. PFC_OK FFD threshold vs. TJ
- Figure 20. Multiplier characteristics at VFF = 1 V
- Figure 21. Multiplier characteristics at VFF = 3 V
- Figure 22. Multiplier gain vs. TJ
- Figure 23. Gate drive clamp vs. TJ
- Figure 24. Gate drive output saturation vs. TJ
- Figure 25. Delay to output vs. TJ
- Figure 26. Start-up timer period vs. TJ
- 6 Application information
- 7 Application examples and ideas
- Figure 34. Demonstration board EVL6564-100W, wide-range mains: electrical schematic
- Figure 35. L6564 100W TM PFC: compliance to EN61000-3-2 standard
- Figure 36. L6564 100W TM PFC: compliance to JEITA-MITI standard
- Figure 37. L6564 100 W TM PFC: input current waveform at 230 - 50 Hz - 100 W load
- Figure 38. L6564 100W TM PFC: input current waveform at 100 V - 50 Hz - 100 W load
- 8 Package mechanical data
- 9 Order codes
- 10 Revision history
DocID16202 Rev 5 19/33
L6564 Application information
33
6.2 Feedback failure protection (FFP)
The OVP function described above handles “normal” overvoltage conditions, i.e. those
resulting from an abrupt load/line change or occurring at startup. In case the overvoltage is
generated by a feedback disconnection, for instance when the upper resistor of the output
divider (R1) fails open, the comparator detects the voltage at the INV pin. If the voltage is
lower than 1.66 V and the OVP is active, the FFP is triggered, the gate drive activity is
immediately stopped, the device is shut down, its quiescent consumption is reduced below
180 µA and the condition is latched as long as the supply voltage of the IC is above the
UVLO threshold. To restart the system it is necessary to recycle the input power, so that the
V
CC
voltage of the L6564 device goes below 6 V.
The PFC_OK pin doubles its function as a not-latched IC disable: a voltage below 0.23 V
will shut down the IC, reducing its consumption below 2 mA. To restart the IC simply let the
voltage at the pin go above 0.27 V.
Note that these functions offer complete protection against not only feedback loop failures
or erroneous settings, but also against a failure of the protection itself. Either the resistor of
the PFC_OK divider failing short or open or a PFC_OK pin floating will result in shutting
down the IC and stopping the preregulator.
6.3 Voltage feed-forward
The power stage gain of PFC preregulators varies with the square of the RMS input voltage.
So does the crossover frequency fc of the overall open-loop gain because the gain has
a single pole characteristic. This leads to large trade-off in the design.
For example, setting the gain of the error amplifier to get fc = 20 Hz at 264 Vac means
having fc 4 Hz at 88 Vac, resulting in a sluggish control dynamics. Additionally, the slow
control loop causes large transient current flow during rapid line or load changes that are
limited by the dynamics of the multiplier output. This limit is considered when selecting the
sense resistor to let the full load power pass under minimum line voltage conditions, with
some margin. But a fixed current limit allows excessive power input at high line, whereas
a fixed power limit requires the current limit to vary inversely with the line voltage.
Voltage feed-forward can compensate for the gain variation with the line voltage and allow
minimizing all of the above-mentioned issues. It consists of deriving a voltage proportional to
the input RMS voltage, feeding this voltage into a squarer/divider circuit (1/V
2
corrector) and
providing the resulting signal to the multiplier that generates the current reference for the
inner current control loop (see Figure 28).