Datasheet
Table Of Contents
- Figure 1. Block diagram
- 1 Description
- 2 Maximum ratings
- 3 Pin connection
- 4 Electrical characteristics
- 5 Typical electrical performance
- Figure 3. IC consumption vs. VCC
- Figure 4. IC consumption vs. TJ
- Figure 5. VCC Zener voltage vs. TJ
- Figure 6. Startup and UVLO vs. TJ
- Figure 7. Feedback reference vs. TJ
- Figure 8. E/A output clamp levels vs. TJ
- Figure 9. UVLO saturation vs. TJ
- Figure 10. OVP levels vs. TJ
- Figure 11. Inductor saturation threshold vs. TJ
- Figure 12. Vcs clamp vs. TJ
- Figure 13. ZCD sink/source capability vs. TJ
- Figure 14. ZCD clamp level vs. TJ
- Figure 15. R discharge vs. TJ
- Figure 16. Line drop detection threshold vs. TJ
- Figure 17. VMULTpk - VVFF dropout vs. TJ
- Figure 18. PFC_OK threshold vs. TJ
- Figure 19. PFC_OK FFD threshold vs. TJ
- Figure 20. Multiplier characteristics at VFF = 1 V
- Figure 21. Multiplier characteristics at VFF = 3 V
- Figure 22. Multiplier gain vs. TJ
- Figure 23. Gate drive clamp vs. TJ
- Figure 24. Gate drive output saturation vs. TJ
- Figure 25. Delay to output vs. TJ
- Figure 26. Start-up timer period vs. TJ
- 6 Application information
- 7 Application examples and ideas
- Figure 34. Demonstration board EVL6564-100W, wide-range mains: electrical schematic
- Figure 35. L6564 100W TM PFC: compliance to EN61000-3-2 standard
- Figure 36. L6564 100W TM PFC: compliance to JEITA-MITI standard
- Figure 37. L6564 100 W TM PFC: input current waveform at 230 - 50 Hz - 100 W load
- Figure 38. L6564 100W TM PFC: input current waveform at 100 V - 50 Hz - 100 W load
- 8 Package mechanical data
- 9 Order codes
- 10 Revision history
Application information L6564
18/33 DocID16202 Rev 5
6 Application information
6.1 Overvoltage protection
Normally, the voltage control loop keeps the output voltage V
O
of the PFC preregulator close
to its nominal value, set by the ratio of the resistors R1 and R2 of the output divider.
A pin of the device (PFC_OK) has been dedicated to monitor the output voltage with
a separate resistor divider (R3 high, R4 low, see Figure 27). This divider is selected so that
the voltage at the pin reaches 2.5 V if the output voltage exceeds a preset value, usually
larger than the maximum V
O
that can be expected.
Example:
V
O
= 400 V, V
OX
= 434 V. Select: R3 = 8.8 M; then: R4 = 8.8 M· 2.5/(434-2.5) = 51 k.
When this function is triggered, the gate drive activity is immediately stopped until the
voltage on the pin PFC_OK drops below 2.4 V. Notice that the R1, R2, R3 and R4 can be
selected without any constraints. The unique criterion is that both dividers have to sink
a current from the output bus which needs to be significantly higher than the bias current of
both the INV and PFC_OK pins.
Figure 27. Output voltage setting, OVP and FFP functions: internal block diagram
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