Datasheet

Table Of Contents
DocID16202 Rev 5 17/33
L6564 Typical electrical performance
33
Figure 24. Gate drive output saturation vs. T
J
Figure 25. Delay to output vs. T
J
0
2
4
6
8
10
12
-50 -25 0 25 50 75 100 125 150 175
Tj (C)
V
Low level
High level
T D (H - L ) (n s)
Figure 26. Start-up timer period vs. T
J
0
50
100
150
200
250
300
350
400
450
-50 -25 0 25 50 75 100 125 150 175
Tj (C)
Ti me (us)
Fi r s t C i c l e
Timer
Aft e r OC P