Datasheet

Application information L6563 - L6563A
22/39
Figure 38. THD optimization: standard TM PFC controller (left side) and L6563/A
(right side)
Essentially, the circuit artificially increases the ON-time of the power switch with a positive
offset added to the output of the multiplier in the proximity of the line voltage zero-crossings.
This offset is reduced as the instantaneous line voltage increases, so that it becomes
negligible as the line voltage moves toward the top of the sinusoid. Furthermore the offset is
modulated by the voltage on the V
FF
pin (see Section 6.3 on page 18 section) so as to have
little offset at low line, where energy transfer at zero crossings is typically quite good, and a
larger offset at high line where the energy transfer gets worse.
The effect of the circuit is shown in Figure 38, where the key waveforms of a standard TM
PFC controller are compared to those of this chip.
To take maximum benefit from the THD optimizer circuit, the high-frequency filter capacitor
after the bridge rectifier should be minimized, compatibly with EMI filtering needs. A large
capacitance, in fact, introduces a conduction dead-angle of the AC input current in itself -
even with an ideal energy transfer by the PFC pre-regulator - thus reducing the effectiveness
of the optimizer circuit.
Imains
Vdrain
Imains
Vdrain
Input current Input current
MOSFET's drain voltage
MOSFET's drain voltage
Rectified mains voltage Rectified mains voltage
Input current
Input current