Datasheet
Table Of Contents
- Figure 1. Packages
- Table 1. Order Codes
- 1 Features
- 1.1 APPLICATIONS
- 2 Description
- Figure 2. Block Diagram
- Table 2. Absolute Maximum Ratings
- Figure 3. Pin Connection (Top view)
- Table 3. Thermal Data
- Table 4. Pin Description
- Table 5. Electrical Characteristics (Tj = -25 to 125C, VCC = 12, CO = 1 nF; unless otherwise specified)
- 3 Typical Electrical Characteristics
- Figure 4. Supply current vs. Supply voltage
- Figure 5. Start-up & UVLO vs. Tj
- Figure 6. IC consumption vs. Tj
- Figure 7. Vcc Zener voltage vs. Tj
- Figure 8. Feedback reference vs. Tj
- Figure 9. OVP current vs. Tj
- Figure 10. E/A output clamp levels vs. Tj
- Figure 11. Delay-to-output vs. Tj
- Figure 12. Multiplier characteristic
- Figure 13. Multiplier gain vs. Tj
- Figure 14. Vcs clamp vs. Tj
- Figure 15. Start-up timer vs. Tj
- Figure 16. ZCD clamp levels vs. Tj
- Figure 17. ZCD source capability vs. Tj
- Figure 18. Gate-drive output low saturation
- Figure 19. Gate-drive output high saturation
- Figure 20. Gate-drive clamp vs. Tj
- Figure 21. UVLO saturation vs. Tj
- 4 Application Information
- 4.1 Overvoltage protection
- 4.2 THD optimizer circuit
- Figure 22. THD optimization: standard TM PFC controller (left side) and L6562 (right side)
- Figure 23. Typical application circuit (250W, Wide-range mains)
- Figure 24. Demo board (EVAL6562-80W, Wide-range mains): Electrical schematic
- Figure 25. EVAL6562-80W: PCB and component layout (Top view, real size: 57 x 108 mm)
- Table 6. EVAL6562N: Evaluation results at full load
- Table 7. EVAL6562N: Evaluation results at half load
- Table 8. EVAL6562N: No-load measurements
- Figure 26. Line filter (not tested for EMI compliance) used for EVAL6562N evaluation
- 5 Package Information
- Figure 27. DIP-8 Mechanical Data & Package Dimensions
- Figure 28. SO-8 Mechanical Data & Package Dimensions
- 6 Revision History
- Table 9. Revision History

L6562
6/16
Figure 8. Feedback reference vs. T
j
Figure 9. OVP current vs. T
j
Figure 10. E/A output clamp levels vs. T
j
Figure 11. Delay-to-output vs. T
j
Figure 12. Multiplier characteristic
Figure 13. Multiplier gain vs. T
j
V
REF
(V)
-50 0 50 100 150
2.4
2.45
2.5
2.55
2.6
Vcc = 12 V
Tj (°C)
I
OVP
(µA)
-50 0 50 100 150
39
39.5
40
40.5
41
Vcc = 12 V
Tj (°C)
Tj (°C)
Vpin2
(V)
-50 0 50 100 150
2
3
4
5
6
Upper clamp
Lower clamp
Vcc = 12 V
Tj (°C)
t
D(H-L)
(ns)
-50 0 50 100 150
0
100
200
300
400
500
Vcc = 12 V
V
MULT
(pin 3) (V)
V
COMP
(pin 2)
(V)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
0
V
CS
(pin 4)
2.6
3.0
3.2
4
.
5
5.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
(V)
4.0
2.8
upper voltage
clamp
3.5
Tj (°C)
K
-50 0 50 100 150
0
0.2
0.4
0.6
0.8
1
Vcc = 12 V
V
COMP
=4 V
V
MULT
=1V