Datasheet
Table Of Contents
- Figure 1. Packages
- Table 1. Order Codes
- 1 Features
- 1.1 APPLICATIONS
- 2 Description
- Figure 2. Block Diagram
- Table 2. Absolute Maximum Ratings
- Figure 3. Pin Connection (Top view)
- Table 3. Thermal Data
- Table 4. Pin Description
- Table 5. Electrical Characteristics (Tj = -25 to 125C, VCC = 12, CO = 1 nF; unless otherwise specified)
- 3 Typical Electrical Characteristics
- Figure 4. Supply current vs. Supply voltage
- Figure 5. Start-up & UVLO vs. Tj
- Figure 6. IC consumption vs. Tj
- Figure 7. Vcc Zener voltage vs. Tj
- Figure 8. Feedback reference vs. Tj
- Figure 9. OVP current vs. Tj
- Figure 10. E/A output clamp levels vs. Tj
- Figure 11. Delay-to-output vs. Tj
- Figure 12. Multiplier characteristic
- Figure 13. Multiplier gain vs. Tj
- Figure 14. Vcs clamp vs. Tj
- Figure 15. Start-up timer vs. Tj
- Figure 16. ZCD clamp levels vs. Tj
- Figure 17. ZCD source capability vs. Tj
- Figure 18. Gate-drive output low saturation
- Figure 19. Gate-drive output high saturation
- Figure 20. Gate-drive clamp vs. Tj
- Figure 21. UVLO saturation vs. Tj
- 4 Application Information
- 4.1 Overvoltage protection
- 4.2 THD optimizer circuit
- Figure 22. THD optimization: standard TM PFC controller (left side) and L6562 (right side)
- Figure 23. Typical application circuit (250W, Wide-range mains)
- Figure 24. Demo board (EVAL6562-80W, Wide-range mains): Electrical schematic
- Figure 25. EVAL6562-80W: PCB and component layout (Top view, real size: 57 x 108 mm)
- Table 6. EVAL6562N: Evaluation results at full load
- Table 7. EVAL6562N: Evaluation results at half load
- Table 8. EVAL6562N: No-load measurements
- Figure 26. Line filter (not tested for EMI compliance) used for EVAL6562N evaluation
- 5 Package Information
- Figure 27. DIP-8 Mechanical Data & Package Dimensions
- Figure 28. SO-8 Mechanical Data & Package Dimensions
- 6 Revision History
- Table 9. Revision History

L6562
4/16
(1) All parameters are in tracking
(2) The multiplier output is given by:
(3) Parameters guaranteed by design, functionality tested in production.
G
v
Voltage Gain Open loop 60 80 dB
GB Gain-Bandwidth Product 1 MHz
I
COMP
Source Current V
COMP
= 4V, V
INV
= 2.4 V -2 -3.5 -5 mA
Sink Current V
COMP
= 4V, V
INV
= 2.6 V 2.5 4.5 mA
V
COMP
Upper Clamp Voltage I
SOURCE
= 0.5 mA 5.3 5.7 6 V
Lower Clamp Voltage
I
SINK
= 0.5 mA
(1)
2.12.252.4 V
CURRENT SENSE COMPARATOR
I
CS
Input Bias Current V
CS
= 0 -1 µA
t
d(H-L)
Delay to Output
200 350 ns
V
CS clamp
Current sense reference clamp V
COMP
= Upper clamp 1.6 1.7 1.8 V
V
CSoffset
Current sense offset V
MULT
= 0 30 mV
V
MULT
= 2.5V 5
ZERO CURRENT DETECTOR
V
ZCDH
Upper Clamp Voltage I
ZCD
= 2.5 mA 5.0 5.7 6.5 V
V
ZCDL
Lower Clamp Voltage I
ZCD
= -2.5 mA 0.3 0.65 1 V
V
ZCDA
Arming Voltage
(positive-going edge)
(3)
2.1 V
V
ZCDT
Triggering Voltage
(negative-going edge)
(3)
1.6 V
I
ZCDb
Input Bias Current
V
ZCD
= 1 to 4.5 V
2µA
I
ZCDsrc
Source Current Capability -2.5 -5.5 mA
I
ZCDsnk
Sink Current Capability 2.5 mA
V
ZCDdis
Disable threshold 150 200 250 mV
V
ZCDen
Restart threshold 350 mV
I
ZCDres
Restart Current after Disable 30 75 µA
STARTER
t
START
Start Timer period
75 130 300 µs
OUTPUT OVERVOLTAGE
I
OVP
Dynamic OVP triggering current 35 40 45 µA
Hys Hysteresis
(3)
30 µA
Static OVP threshold
(1)
2.12.252.4 V
GATE DRIVER
V
OH
Dropout Voltage
I
GDsource
= 20 mA
22.6
I
GDsource
= 200 mA
2.5 3 V
V
OL
I
GDsink
= 200 mA
0.9 1.9 V
t
f
Voltage Fall Time 30 70 ns
t
r
Voltage Rise Time 40 80 ns
V
Oclamp
Output clamp voltage I
GDsource
= 5mA; Vcc = 20V
10 12 15 V
UVLO saturation V
CC
= 0 to V
CCon
, I
sink
=10mA 1.1 V
Table 5. Electrical Characteristics (continued)
(T
j
= -25 to 125°C, V
CC
= 12, C
O
= 1 nF; unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
V
cs
KV
MULT
V
COMP
2.5–()⋅⋅=