Datasheet

ManualsBrandsSTMICROELECTRONICS ManualsPMICsPMIC - PFC 40 µA SO 8

Table Of Contents

Figure 1. Packages
Table 1. Order Codes
1 Features
1.1 APPLICATIONS
2 Description
Figure 2. Block Diagram
Table 2. Absolute Maximum Ratings
Figure 3. Pin Connection (Top view)
Table 3. Thermal Data
Table 4. Pin Description
Table 5. Electrical Characteristics (Tj = -25 to 125C, VCC = 12, CO = 1 nF; unless otherwise specified)
3 Typical Electrical Characteristics
Figure 4. Supply current vs. Supply voltage
Figure 5. Start-up & UVLO vs. Tj
Figure 6. IC consumption vs. Tj
Figure 7. Vcc Zener voltage vs. Tj
Figure 8. Feedback reference vs. Tj
Figure 9. OVP current vs. Tj
Figure 10. E/A output clamp levels vs. Tj
Figure 11. Delay-to-output vs. Tj
Figure 12. Multiplier characteristic
Figure 13. Multiplier gain vs. Tj
Figure 14. Vcs clamp vs. Tj
Figure 15. Start-up timer vs. Tj
Figure 16. ZCD clamp levels vs. Tj
Figure 17. ZCD source capability vs. Tj
Figure 18. Gate-drive output low saturation
Figure 19. Gate-drive output high saturation
Figure 20. Gate-drive clamp vs. Tj
Figure 21. UVLO saturation vs. Tj
4 Application Information
4.1 Overvoltage protection
4.2 THD optimizer circuit
Figure 22. THD optimization: standard TM PFC controller (left side) and L6562 (right side)
Figure 23. Typical application circuit (250W, Wide-range mains)
Figure 24. Demo board (EVAL6562-80W, Wide-range mains): Electrical schematic
Figure 25. EVAL6562-80W: PCB and component layout (Top view, real size: 57 x 108 mm)
Table 6. EVAL6562N: Evaluation results at full load
Table 7. EVAL6562N: Evaluation results at half load
Table 8. EVAL6562N: No-load measurements
Figure 26. Line filter (not tested for EMI compliance) used for EVAL6562N evaluation
5 Package Information
Figure 27. DIP-8 Mechanical Data & Package Dimensions
Figure 28. SO-8 Mechanical Data & Package Dimensions
6 Revision History
Table 9. Revision History

13/16

L6562

5 Package Information

In order to meet environmental requirements, ST offers these devices in ECOPACK

packages. These

packages have a Lead-free second level interconnect. The category of second Level Interconnect is

marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The

maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an

ST trademark.

ECOPACK specifications are available at: www.st.com.

Figure 27. DIP-8 Mechanical Data & Package Dimensions

OUTLINE AND

MECHANICAL DATA

DIM.

mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A3.32 0.131

a1 0.51 0.020

B 1.15 1.65 0.045 0.065

b 0.356 0.55 0.014 0.022

b1 0.204 0.304 0.008 0.012

D 10.92 0.430

E 7.95 9.75 0.313 0.384

e2.54 0.100

e3 7.62 0.300

e4 7.62 0.300

F 6.6 0.260

I 5.08 0.200

L 3.18 3.81 0.125 0.150

Z 1.52 0.060

DIP-8