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L6562

November 2005

1Features

■ REALISED IN BCD TECHNOLOGY

■ TRANSITION-MODE CONTROL OF PFC PRE-

REGULATORS

■ PROPRIETARY MULTIPLIER DESIGN FOR

MINIMUM THD OF AC INPUT CURRENT

■ VERY PRECISE ADJUSTABLE OUTPUT

OVERVOLTAGE PROTECTION

■ ULTRA-LOW (≤70µA) START-UP CURRENT

■ LOW (≤4 mA) QUIESCENT CURRENT

■ EXTENDED IC SUPPLY VOLTAGE RANGE

■ ON-CHIP FILTER ON CURRENT SENSE

■ DISABLE FUNCTION

■ 1% (@ Tj = 25 °C) INTERNAL REFERENCE

VOLTAGE

■

-600/+800mA TOTEM POLE GATE DRIVER WITH

UVLO PULL-DOWN AND VOLTAGE CLAMP

■ DIP-8/SO-8 PACKAGES ECOPACK

1.1 APPLICATIONS

■ PFC PRE-REGULATORS FOR:

– IEC61000-3-2 COMPLIANT SMPS (TV,

DESKTOP PC, MONITOR) UP TO 300W

– HI-END AC-DC ADAPTER/CHARGER

– ENTRY LEVEL SERVER & WEB SERVER

2 Description

The L6562 is a current-mode PFC controller oper-

ating in Transition Mode (TM). Pin-to-pin compati-

ble with the predecessor L6561, it offers improved

performance.

TRANSITION-MODE PFC CONTROLLER

Figure 2. Block Diagram

MULTIPLIER AND

THD OPTIMIZER

REF2

OVERVOLTAGE

DETECTION

VOLTAGE

REGULATOR

UVLO

INTERNAL

SUPPLY 7V

2.5V

DRIVER

STARTER

ZERO CURRENT

DETECTOR

DISABLE

2.1 V

1.6 V

VCC

23 4

ZCD

INV

COMP MULT CS

GND

25 V

40K

5pF

15 V

Starter

stop

Rev. 8

gure 1.

ages

Table 1. Order Codes

Part Number Package

L6562N DIP-8

L6562D SO-8

L6562DTR Tape & Reel

DIP-8

SO-8

Summary of content (16 pages)

PAGE 1
L6562 TRANSITION-MODE PFC CONTROLLER 1 ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Features Figure 1.
PAGE 2
L6562 2 Description (continued) The highly linear multiplier includes a special circuit, able to reduce AC input current distortion, that allows wide-range-mains operation with an extremely low THD, even over a large load range. The output voltage is controlled by means of a voltage-mode error amplifier and a precise (1% @Tj = 25°C) internal voltage reference.
PAGE 3
L6562 Table 4. Pin Description N° Pin Function 1 INV Inverting input of the error amplifier. The information on the output voltage of the PFC preregulator is fed into the pin through a resistor divider. 2 COMP Output of the error amplifier. A compensation network is placed between this pin and INV (pin #1) to achieve stability of the voltage control loop and ensure high power factor and low THD. 3 MULT Main input to the multiplier.
PAGE 4
L6562 Table 5. Electrical Characteristics (continued) (Tj = -25 to 125°C, VCC = 12, CO = 1 nF; unless otherwise specified) Symbol Parameter Gv Voltage Gain GB Gain-Bandwidth Product Test Condition Open loop Min. Typ. Max. Unit 60 80 dB 1 MHz ICOMP Source Current Sink Current VCOMP = 4V, VINV = 2.6 V 2.5 4.5 VCOMP Upper Clamp Voltage ISOURCE = 0.5 mA 5.3 5.7 6 V Lower Clamp Voltage ISINK = 0.5 mA (1) 2.1 2.25 2.4 V -1 µA 200 350 ns 1.7 1.8 V VCOMP = 4V, VINV = 2.
PAGE 5
L6562 3 Typical Electrical Characteristics Figure 4. Supply current vs. Supply voltage Figure 6. IC consumption vs. Tj Icc 10 [mA] 5 ICC (mA) Operating Quiescent 10 2 5 Disabled or during OVP 1 1 0.5 0.5 0.1 0.2 0.05 Co = 1nF f = 70 kHz Tj = 25°C 0.01 0.005 0.1 5 10 15 20 Before start-up 0.05 0 0 Vcc = 12 V Co = 1 nF f = 70 kHz 25 0.02 -50 0 Vcc(V) 100 150 Tj (°C) Figure 7. Vcc Zener voltage vs. Tj Figure 5. Start-up & UVLO vs. Tj VccZ 28 (V) 12.
PAGE 6
L6562 Figure 8. Feedback reference vs. Tj Figure 11. Delay-to-output vs. Tj VREF 2.6 (V) tD(H-L) 500 (ns) Vcc = 12 V Vcc = 12 V 400 2.55 300 2.5 200 2.45 100 2.4 -50 0 50 100 0 -50 150 0 100 150 Tj (°C) Tj (°C) Figure 9. OVP current vs. Tj Figure 12. Multiplier characteristic VCOMP (pin 2) (V) VCS (pin 4) (V) upper voltage 41 (µA) clamp Vcc = 12 V 1.6 40.5 3.5 5.0 1.4 4. 5 IOVP 50 1.2 4.0 3.2 1.0 40 0.8 3.0 0.6 39.5 0.4 2.8 0.2 2.
PAGE 7
L6562 Figure 14. Vcs clamp vs. Tj Figure 17. ZCD source capability vs. Tj VCSx 2 (V) IZCDsrc 0 (mA) Vcc = 12 V VZCD = lower clamp 1.8 -2 1.6 -4 1.4 1.2 1 -50 Vcc = 12 V VCOMP= Upper clamp 0 -6 50 100 -8 -50 150 0 50 Figure 15. Start-up timer vs. Tj Tstart 150 (µs) 100 150 Tj (°C) Tj (°C) Figure 18. Gate-drive output low saturation Vpin7 [V] 4 Vcc = 12 V Tj = 25 °C Vcc = 11 V SINK 140 3 130 2 120 1 110 0 100 -50 0 50 100 150 0 200 800 1,000 Figure 19.
PAGE 8
L6562 Figure 20. Gate-drive clamp vs. Tj Figure 21. UVLO saturation vs. Tj Vpin7 clamp 15 (V) Vpin7 (V) 1.1 Vcc = 0 V Vcc = 20 V 1 14 0.9 13 0.8 12 0.7 11 10 -50 0.6 0 50 100 150 0.5 -50 50 100 150 Tj (°C) Tj (°C) 4 0 Application Information 4.1 Overvoltage protection Under steady-state conditions, the voltage control loop keeps the output voltage Vo of a PFC pre-regulator close to its nominal value, set by the resistors R1 and R2 of the output divider.
PAGE 9
L6562 When the load of a PFC pre-regulator is very low, the output voltage tends to stay steadily above the nominal value, which cannot be handled by the Dynamic OVP. If this occurs, however, the error amplifier output will saturate low; hence, when this is detected, the external power transistor is switched off and the IC put in an idle state (Static OVP). Normal operation is resumed as the error amplifier goes back into its linear region.
PAGE 10
L6562 the output of the multiplier in the proximity of the line voltage zero-crossings. This offset is reduced as the instantaneous line voltage increases, so that it becomes negligible as the line voltage moves toward the top of the sinusoid. To maximally benefit from the THD optimizer circuit, the high-frequency filter capacitor after the bridge rectifier should be minimized, compatibly with EMI filtering needs.
PAGE 11
L6562 Figure 25. EVAL6562-80W: PCB and component layout (Top view, real size: 57 x 108 mm) Table 6. EVAL6562N: Evaluation results at full load Vin (VAC) Pin (W) Vo (VDC) ∆Vo(Vpk-pk) Po (W) η (%) PF THD (%) 85 86.4 394.79 12.8 80.16 92.8 0.998 3.6 110 84.6 394.86 12.8 80.20 94.8 0.996 4.2 135 83.8 394.86 12.8 80.20 95.7 0.991 4.9 175 83.2 394.87 15.5 80.20 96.4 0.981 6.5 220 82.9 394.87 15.7 80.20 96.7 0.956 7.8 265 82.7 394.87 15.9 80.20 97.0 0.915 9.
PAGE 12
L6562 Table 8. EVAL6562N: No-load measurements (*) Vin (VAC) Pin (W) Vo (VDC) ∆Vo(Vpk-pk) Po (W) 85 0.4 396.77 0.45 0 110 0.3 396.82 0.55 0 135 0.3 396.83 0.60 0 175 (*) 0.4 396.90 1.00 0 220 (*) 0.4 396.95 1.40 0 265 (*) 0.5 396.98 1.65 0 Vcc = 12V supplied externally Figure 26. Line filter (not tested for EMI compliance) used for EVAL6562N evaluation to the AC source B81133 680 nF, X2 EPCOS B81133 470 nF, X2 EPCOS B82732 47 mH, 1.
PAGE 13
L6562 5 Package Information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 27.
PAGE 14
L6562 Figure 28. SO-8 Mechanical Data & Package Dimensions mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 A2 1.10 1.65 0.043 0.065 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 4.80 5.00 0.189 0.197 4.00 0.15 D (1) E 3.80 e 1.27 0.157 0.050 H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 k ddd OUTLINE AND MECHANICAL DATA 0˚ (min.), 8˚ (max.) 0.10 0.
PAGE 15
L6562 6 Revision History Table 9. Revision History Date Revision Description of Changes January 2004 5 First Issue June 2004 6 Modified the Style-look in compliance with the “Corporate Technical Publications Design Guide”. Changed input of the power amplifier connected to Multiplier (Fig. 2). May 2005 7 Modified Table 2: Absolute Maximim Ratings. November 2005 8 Added in Section 5 the ECOPACK® certicate of conformity.
PAGE 16
L6562 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice.