Datasheet

L6390 Smart shutdown function
Doc ID 14493 Rev 7 15/26
In common overcurrent protection architectures the comparator output is usually connected
to the SD input and an RC network is connected to this SD/OD line in order to provide a
mono-stable circuit, which implements a protection time that follows the fault condition.
Differently from the common fault detection systems, the L6390 smart shutdown
architecture allows immediate turn-off of the outputs of the gate driver in the case of fault, by
minimizing the propagation delay between the fault detection event and the actual output
switch-off. In fact, the time delay between the fault detection and the output turn-off is no
longer dependent on the value of the external RC network connected to the SD/OD pin. In
the smart shutdown circuitry the fault signal has a preferential path which directly switches
off the outputs after the comparator triggering. At the same time the internal logic turns on
the open drain output and holds it on until the SD voltage goes below the SD logic input
lower threshold. When such threshold is reached, the open drain output is turned off,
allowing the external pull-up to recharge the capacitor. The driver outputs restart following
the input pins as soon as the voltage at the SD/OD pin reaches the higher threshold of the
SD logic input. The smart shutdown system provides the possibility to increase the time
constant of the external RC network (that determines the disable time after the fault event)
up to very large values without increasing the delay time of the protection.
Any external signal provided to the SD pin is not latched and can be used as control signal
in order to perform, for instance, PWM chopping through this pin. In fact when a PWM signal
is applied to the SD input and the logic inputs of the gate driver are stable, the outputs
switch from the low level to the state defined by the logic inputs and vice versa.
In some applications it may be useful to latch the driver in the shutdown condition for an
arbitrary time, until the controller decides to reset it to normal operation. This may, for
example, be achieved with a circuit similar to the one shown in Figure 7. When the open
drain starts pulling down the SD/OD pin, the external latch turns on and keeps the pin to
GND, preventing it from being pulled up again once the SD logic input lower threshold is
reached and the internal open drain turns off. One pin of the controller is used to release the
external latch, and one to externally force a shutdown condition and also to read the status
of the SD/OD pin.
Figure 7. Protection latching example circuit
In applications using only one L6390 for the protection of several different legs (such as a
single-shunt inverter, for example) it may be useful to implement the resistor divider shown
in Figure 8. This simple network allows the pushing of the SD pins of the other devices to a
voltage lower than L6390 V
il
, so that each device can reach its low logic level regardless of
part-to-part variations of the thresholds.
SD_reset
SD_force/sense
GND
VDD
µC
3.3 / 5 V
3.3 / 5 V
R1
R2
R3
R4
HVG
OUT
LVG
VBOOT
OP+
OP-
OPOUT
DT
CP+
L6390
SD/OD
GND
VCC
HIN
LIN
+
+
-
VCC
To other driver/devices
AM12949v1
20 K
1.5 K
Ω
Ω
2.2 K
Ω
20 K
Ω