Datasheet

Circuit description L6229Q
20/28 Doc ID 15209 Rev 3
5.7 Non-dissipative overcurrent detection and protection
The L6229Q integrates an overcurrent detection circuit (OCD) for full protection. This circuit
provides output-to-output and output-to-ground short circuit protection as well. With this
internal over current detection, the external current sense resistor normally used and its
associated power dissipation are eliminated. Figure 19 shows a simplified schematic for the
overcurrent detection circuit.
To implement the over current detection, a sensing element that delivers a small but precise
fraction of the output current is implemented with each high side power MOS. Since this
current is a small fraction of the output current there is very little additional power
dissipation. This current is compared with an internal reference current I
REF
. When the
output current reaches the detection threshold (typically I
SOVER
= 2.8 A) the OCD
comparator signals a fault condition. When a fault condition is detected, an internal open
drain MOS with a pull down capability of 4 mA connected to pin DIAG is turned on.
The pin DIAG can be used to signal the fault condition to a μC or to shut down the three-
phase bridge simply by connecting it to pin EN and adding an external R-C (see R
EN
, C
EN
).
Figure 19. Overcurrent protection simplified schematic
Figure 20 shows the overcurrent detection operation. The disable time t
DISABLE
before
recovering normal operation can be easily programmed by means of the accurate
thresholds of the logic inputs. It is affected whether by C
EN
and R
EN
values and its
magnitude is reported in Figure 21. The delay time t
DELAY
before turning off the bridge when
an overcurrent has been detected depends only by C
EN
value. Its magnitude is reported in
Figure 22
C
EN
is also used for providing immunity to pin EN against fast transient noises. Therefore
the value of C
EN
should be chosen as big as possible according to the maximum tolerable
delay time and the R
EN
value should be chosen according to the desired disable time.
The resistor R
EN
should be chosen in the range from 2.2 kΩ to 180 kΩ. Recommended
values for R
EN
and C
EN
are respectively 100 kΩ and 5.6 nF that allow obtaining 200 μs
disable time.
+
OVER TEMPERATURE
I
REF
I
REF
I
1
+I
2
/ n
I
1
/ n
HIGH SIDE DMOS
POWER SENSE
1 cell
POWER SENSE
1 cell
POWER SENSE
1 cell
POWER DMOS
n cells
POWER DMOS
n cells
POWER DMOS
n cells
HIGH SIDE DMOS HIGH SIDE DMOS
OUT
1
OUT
2
VS
A
OUT
3
VS
B
I
1
I
2
I
3
I
2
/ n
I
3
/ n
OCD
COMPARATOR
TO GATE
LOGIC
INTERNAL
OPEN-DRAIN
R
DS(ON)
40Ω TYP.
C
EN
R
EN
DIAG
EN
V
DD
μC or LOGIC
D02IN1381