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L6229

October 2004

1FEATURES

■ OPERATING SUPPLY VOLTAGE FROM 8 TO

52V

■ 2.8A OUTPUT PEAK CURRENT (1.4A DC)

■ R

DS(ON)

0.73Ω TYP. VALUE @ T

= 25 °C

■ OPERATING FREQUENCY UP TO 100KHz

■ NON DISSIPATIVE OVERCURRENT

DETECTION AND PROTECTION

■ DIAGNOSTIC OUTPUT

■ CONSTANT t

OFF

PWM CURRENT

CONTROLLER

■ SLOW DECAY SYNCHR. RECTIFICATION

■ 60° & 120° HALL EFFECT DECODING LOGIC

■ BRAKE FUNCTION

■ TACHO OUTPUT FOR SPEED LOOP

■ CROSS CONDUCTION PROTECTION

■ THERMAL SHUTDOWN

■ UNDERVOLTAGE LOCKOUT

■ INTEGRATED FAST FREEWEELING DIODES

2 DESCRIPTION

The L6229 is a DMOS Fully Integrated Three-Phase

Motor Driver with Overcurrent Protection.

Realized in MultiPower-BCD technology, the device

combines isolated DMOS Power Transistors with

CMOS and bipolar circuits on the same chip.

The device includes all the circuitry needed to drive a

three-phase BLDC motor including: a three-phase

DMOS Bridge, a constant off time PWM Current Con-

troller and the decoding logic for single ended hall

sensors that generates the required sequence for the

power stage.

Available in PowerDIP24 (20+2+2), PowerSO36 and

SO24 (20+2+2) packages, the L6229 features a non-

dissipative overcurrent protection on the high side

Power MOSFETs and thermal shutdown.

DMOS DRIVER FOR

THREE-PHASE BRUSHLESS DC MOTOR

gure 1.

age

Table 1. Order Codes

Part Number Package

L6229N PowerDIP24

L6229PD PowerSO36

L6229PDTR PowerSO36 in Tape & Reel

L6229D SO24

L6229DTR SO24 in Tape & Reel

PowerDIP24

(20+2+2)

PowerSO36

SO24

(20+2+2)

Rev. 3

Summary of content (25 pages)

PAGE 1
L6229 DMOS DRIVER FOR THREE-PHASE BRUSHLESS DC MOTOR 1 ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 2 FEATURES Figure 1. Package OPERATING SUPPLY VOLTAGE FROM 8 TO 52V 2.8A OUTPUT PEAK CURRENT (1.4A DC) RDS(ON) 0.73Ω TYP. VALUE @ Tj = 25 °C OPERATING FREQUENCY UP TO 100KHz NON DISSIPATIVE OVERCURRENT DETECTION AND PROTECTION DIAGNOSTIC OUTPUT CONSTANT tOFF PWM CURRENT CONTROLLER SLOW DECAY SYNCHR.
PAGE 2
L6229 Figure 2. Block Diagram VBOOT VBOOT VBOOT CHARGE PUMP VCP VSA THERMAL PROTECTION OCD1 DIAG OCD OUT1 10V OCD1 OCD2 OCD OCD3 VBOOT EN BRAKE FWD/REV OCD2 H3 HALL-EFFECT SENSORS DECODING LOGIC H2 GATE LOGIC SENSEA VBOOT H1 RCPULSE OUT2 10V TACHO MONOSTABLE VSB OCD3 OUT3 10V TACHO 10V 5V SENSEB PWM VOLTAGE REGULATOR ONE SHOT MONOSTABLE MASKING TIME + SENSE COMPARATOR VREF RCOFF D99IN1095B Table 2.
PAGE 3
L6229 Table 3. Recommended Operating Condition Symbol VS Parameter Test Conditions Supply Voltage VSA = VSB = VS VOD Differential Voltage between: VSA, OUT1, OUT2, SENSEA and VSB, OUT3, SENSEB VSA = VSB = VS; VSENSEA = VSENSEB VREF Voltage Range at pin VREF VSENSE IOUT Voltage Range at pins SENSEA and SENSEB (pulsed tW < trr) (DC) DC Output Current VSA = VSB = VS TJ Operating Junction Temperature fSW Switching Frequency MIN MAX Unit 12 52 V 52 V -0.1 5 V -6 -1 6 1 V V 1.
PAGE 4
L6229 Figure 3. Pin Connections (Top view) GND 1 36 GND N.C. 2 35 N.C. N.C. H1 1 24 H3 N.C. 3 34 DIAG 2 23 H2 VSA 4 33 VSB OUT2 5 32 OUT3 SENSEA 3 22 VCP RCOFF 4 21 OUT2 OUT1 5 20 VSA GND 6 19 GND GND 7 18 GND TACHO 8 17 VSB RCPULSE 9 16 OUT3 SENSEB 10 15 VBOOT FWD/REV 11 14 BRAKE EN 12 13 VREF D01IN1194A N.C. 6 31 N.C.
PAGE 5
L6229 Table 5. Pin Description (continued) PACKAGE SO24/ PowerDIP24 PowerSO36 PIN # PIN # 10 25 SENSEB 11 26 FWD/REV Logic Input Selects the direction of the rotation. HIGH logic level sets Forward Operation, whereas LOW logic level sets Reverse Operation. If not used, it has to be connected to GND or +5V.. 12 27 EN Logic Input Chip Enable. LOW logic level switches OFF all Power MOSFETs. If not used, it has to be connected to +5V.
PAGE 6
L6229 Table 6. Electrical Characteristics (continued) (VS = 48V , Tamb = 25 °C , unless otherwise specified) Symbol Parameter Test Conditions Min Typ Max Unit 1.3 V Source Drain Diodes VSD Forward ON Voltage ISD = 1.4A, EN = LOW 1.15 trr Reverse Recovery Time If = 1.4A 300 ns tfr Forward Recovery Time 200 ns Logic Input (H1, H2, H3, EN, FWD/REV, BRAKE) VIL Low level logic input voltage -0.3 0.
PAGE 7
L6229 Table 6. Electrical Characteristics (continued) (VS = 48V , Tamb = 25 °C , unless otherwise specified) Symbol tPULSE Parameter Test Conditions Monostable of Time Min Typ Max Unit RPUL = 20kΩ ; CPUL =1nF 12 µs RPUL = 100kΩ ; CPUL =1nF 60 µs RTACHO Open Drain ON Resistance 40 60 Ω 2.8 3.
PAGE 8
L6229 3 CIRCUIT DESCRIPTION 3.1 POWER STAGES and CHARGE PUMP The L6229 integrates a Three-Phase Bridge, which consists of 6 Power MOSFETs connected as shown on the Block Diagram. Each Power MOS has an RDS(ON) = 0.73Ω (typical value @25°C) with intrinsic fast freewheeling diode. Switching patterns are generated by the PWM Current Controller and the Hall Effect Sensor Decoding Logic (see relative paragraphs).
PAGE 9
L6229 Figure 7. Logic Input Internal Structure 5V ESD PROTECTION D01IN1329 Figure 8. Pin EN Open Collector Driving DIAG 5V 5V REN OPEN COLLECTOR OUTPUT CEN EN ESD PROTECTION D02IN1378 Figure 9. Pin EN Push-Pull Driving DIAG 5V PUSH-PULL OUTPUT REN EN CEN ESD PROTECTION D02IN1379 3.3 PWM CURRENT CONTROL The L6229 includes a constant off time PWM Current Controller.
PAGE 10
L6229 verse recovery of the freewheeling diodes. The L6229 provides a 1µs Blanking Time tBLANK that inhibits the comparator output so that the current spike cannot prematurely retrigger the monostable. Figure 10. PWM Current Controller Simplified Schematic VSA VSB BLANKING TIME MONOSTABLE TO GATE LOGIC 1µs 5mA FROM THE LOW-SIDE GATE DRIVERS MONOSTABLE SET BLANKER S (0) OUT2 Q (1) OUT3 R DRIVERS + DEAD TIME - OUT1 DRIVERS + DEAD TIME DRIVERS + DEAD TIME + 5V 2.
PAGE 11
L6229 Figure 12 shows the magnitude of the Off Time tOFF versus COFF and ROFF values. It can be approximately calculated from the equations: tRCFALL = 0.6 · ROFF · COFF tOFF = tRCFALL + tDT = 0.6 · ROFF · COFF + tDT where ROFF and COFF are the external component values and tDT is the internally generated Dead Time with: 20KΩ ≤ ROFF ≤ 100KΩ 0.47nF ≤ COFF ≤ 100nF tDT = 1µs (typical value) Therefore: tOFF(MIN) = 6.
PAGE 12
L6229 Figure 13. Area where tON can vary maintaining the PWM regulation. ton(min) [µs] 100 10 1.5µs (typ. value) 1 0.1 1 10 100 Coff [nF] 3.4 SLOW DECAY MODE Figure 14 shows the operation of the bridge in the Slow Decay mode during the Off Time. At any time only two legs of the three-phase bridge are active, therefore only the two active legs of the bridge are shown in the figure and the third leg will be off.
PAGE 13
L6229 3.5 DECODING LOGIC The Decoding Logic section is a combinatory logic that provides the appropriate driving of the three-phase bridge outputs according to the signals coming from the three Hall Sensors that detect rotor position in a 3phase BLDC motor. This novel combinatory logic discriminates between the actual sensor positions for sensors spaced at 60, 120, 240 and 300 electrical degrees.
PAGE 14
L6229 Figure 16. 60° Hall Sensor Sequence. H1 H1 H1 H1 H1 H1 H2 H2 H2 H2 H2 H2 H3 H3 1 =H H3 2 H3 3b 4 H3 H3 5 6b =L 3.6 TACHO A tachometer function consists of a monostable, with constant off time (tPULSE), whose input is one Hall Effect signal (H1). It allows developing an easy speed control loop by using an external op amp, as shown in Figure 18. For component values refer to Application Information section. The monostable output drives an open drain output pin (TACHO).
PAGE 15
L6229 Figure 18. Tachometer Speed Control Loop. H1 RCPULSE TACHO MONOSTABLE VDD CPUL RPUL R3 RDD TACHO C1 R4 VREF R1 VREF CREF2 CREF1 R2 Figure 19. tPULSE versus CPUL and RPUL. 4 1 .10 R PUL = 100kΩ R PUL = 47kΩ 3 1 .
PAGE 16
L6229 3.7 NON-DISSIPATIVE OVERCURRENT DETECTION and PROTECTION The L6229 integrates an Overcurrent Detection Circuit (OCD) for full protection. This circuit provides Output-toOutput and Output-to-Ground short circuit protection as well. With this internal over current detection, the external current sense resistor normally used and its associated power dissipation are eliminated. Figure 20 shows a simplified schematic for the overcurrent detection circuit.
PAGE 17
L6229 Figure 21. Overcurrent Protection Waveforms IOUT ISOVER VEN=VDIAG VDD Vth(ON) Vth(OFF) VEN(LOW) ON OCD OFF ON tDELAY BRIDGE tDISABLE OFF tOCD(ON) tEN(FALL) tOCD(OFF) tEN(RISE) tD(ON)EN tD(OFF)EN D02IN1383 Figure 22. tDISABLE versus CEN and REN. R EN = 220 kΩ 3 1 .1 0 R EN = 100 k Ω R EN = 47 kΩ R EN = 33 kΩ R EN = 10 kΩ tDISABLE [µs] 1 00 10 1 1 10 1 00 C E N [n F ] Figure 23. tDELAY versus CEN. tdelay [µs] 10 1 0.
PAGE 18
L6229 4 APPLICATION INFORMATION A typical application using L6229 is shown in Figure 24. Typical component values for the application are shown in Table 9. A high quality ceramic capacitor (C2) in the range of 100nF to 200nF should be placed between the power pins VSA and VSB and ground near the L6229 to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching.
PAGE 19
L6229 4.1 OUTPUT CURRENT CAPABILITY AND IC POWER DISSIPATION In Figure 25 is shown the approximate relation between the output current and the IC power dissipation using PWM current control. For a given output current the power dissipated by the IC can be easily evaluated, in order to establish which package should be used and how large must be the on-board copper dissipating area to guarantee a safe operating junction temperature (125°C maximum). Figure 25. IC Power Dissipation versus Output Power.
PAGE 20
L6229 Figure 27. PowerDIP24 Junction-Ambient thermal resistance versus on-board copper area. ºC / W On-Board Copper Area 49 48 C o p pe r Are a is o n Bo tto m S id e 47 C o p pe r Are a is o n To p S i de 46 45 44 43 42 41 40 39 1 2 3 4 5 6 7 8 9 10 11 12 s q . cm Figure 28. SO24 Junction-Ambient thermal resistance versus on-board copper area. On-Board Copper Area ºC / W 68 66 64 62 60 C o pp er A re a is o n T op S id e 58 56 54 52 50 48 1 2 3 4 5 6 7 8 9 10 11 12 s q.
PAGE 21
L6229 Figure 30. PowerSO36 Mechanical Data & Package Dimensions DIM. A A2 A4 A5 a1 b c D D1 D2 E E1 E2 E3 E4 e e3 G H h L N s MIN. 3.25 mm TYP. 0.8 MAX. 3.5 3.3 1 MIN. 0.128 0.075 0.38 0.32 16 9.8 0 0.008 0.009 0.622 0.37 14.5 11.1 2.9 6.2 3.2 0.547 0.429 0.031 0.2 1 0.003 0.015 0.012 0.630 0.38 0.039 13.9 10.9 5.8 2.9 0.57 0.437 0.114 0.244 1.259 0.228 0.114 0.65 11.05 0.026 0.435 0.075 0 15.9 0.61 1.1 1.1 0.031 10˚ (max) 8˚ (max) 0.8 OUTLINE AND MECHANICAL DATA MAX. 0.138 0.13 0.
PAGE 22
L6229 Figure 31. PDIP-24 Mechanical Data & Package Dimensions mm DIM. MIN. TYP. A A1 inch MAX. MIN. TYP. 4.320 0.380 A2 0.170 0.015 3.300 0.130 B 0.410 0.460 0.510 0.016 0.018 0.020 B1 1.400 1.520 1.650 0.055 0.060 0.065 c 0.200 0.250 0.300 0.008 0.010 0.012 D 31.62 31.75 31.88 1.245 1.250 1.255 E 7.620 8.260 0.300 e 2.54 E1 6.350 e1 L 6.600 M 0.325 0.100 6.860 0.250 0.260 0.270 0.300 7.620 3.180 OUTLINE AND MECHANICAL DATA MAX. 3.430 0.
PAGE 23
L6229 Figure 32. SO24 Mechanical Data & Package Dimensions mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.10 0.30 0.004 0.012 B 0.33 0.51 0.013 0.200 C 0.23 0.32 0.009 0.013 D (1) 15.20 15.60 0.598 0.614 E 7.40 7.60 0.291 0.299 e 1.27 10.0 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.40 1.27 0.016 0.050 ddd Weight: 0.60gr 0.050 H k OUTLINE AND MECHANICAL DATA 0˚ (min.), 8˚ (max.) 0.10 0.
PAGE 24
L6229 Table 10. Revision History Date Revision September 2003 1 First Issue January 2004 2 Migration from ST-Press dms to EDOCS. October 2004 3 Updated the style graphic form.
PAGE 25
L6229 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice.