Datasheet

L6226Q Application information
Doc ID 14335 Rev 5 17/29
5 Application information
A typical application using L6226Q is shown in Figure 14. Typical component values for the
application are shown in Ta b l e 8. A high quality ceramic capacitor in the range of 100 to 200
nF should be placed between the power pins (VS
A
and VS
B
) and ground near the L6226Q
to improve the high frequency filtering on the power supply and reduce high frequency
transients generated by the switching. The capacitors connected from the EN
A
/OCD
A
and
EN
B
/OCD
B
nodes to ground set the shut down time for the bridge A and bridge B
respectively when an over current is detected (see overcurrent protection). The two current
sources (SENSE
A
and SENSE
B
) should be connected to power ground with a trace length
as short as possible in the layout. To increase noise immunity, unused logic pins are best
connected to 5 V (high logic level) or GND (low logic level) (see pin description). It is
recommended to keep power ground and Signal Ground separated on PCB.
Table 8. Component values for typical application
Component Value
C
1
100 nF
C
2
100 µF
C
BOOT
220 nF
C
P
10 nF
C
ENA
5.6 nF
C
ENB
5.6 nF
C
REF
68 nF
D
1
1N4148
D
2
1N4148
R
CLA
5 kΩ
R
CLB
5 kΩ
R
ENA
100 kΩ
R
ENB
100 kΩ