Datasheet

Circuit description L6226Q
12/29 Doc ID 14335 Rev 5
4.3 Truth table
4.4 Non-dissipative overcurrent detection and protection
An overcurrent detection circuit (OCD) is integrated. This circuit can be used to provides
protection against a short circuit to ground or between two phases of the bridge as well as a
roughly regulation of the load current. With this internal over current detection, the external
current sense resistor normally used and its associated power dissipation are eliminated.
Figure 9 shows a simplified schematic of the overcurrent detection circuit for the bridge A.
bridge B is provided of an analogous circuit.
To implement the over current detection, a sensing element that delivers a small but precise
fraction of the output current is implemented with each high side power MOS. Since this
current is a small fraction of the output current there is very little additional power
dissipation. This current is compared with an internal reference current I
REF
. When the
output current reaches the detection threshold Isover the OCD comparator signals a fault
condition. When a fault condition is detected, an internal open drain MOS with a pull down
capability of 4 mA connected to OCD pin is turned on. Figure 10 shows the OCD operation.
This signal can be used to regulate the output current simply by connecting the OCD pin to
EN pin and adding an external R-C as shown in Figure 9. The off time before recovering
normal operation can be easily programmed by means of the accurate thresholds of the
logic inputs.
I
REF
and, therefore, the output current detection threshold are selectable by R
CL
value,
following the equations:
● Isover = 2.8 A ± 30 % at -25 °C < T
J
< 125 °C if R
CL
= 0 Ω
(PROGCL connected to GND)
● Isover = ±10 % at -25 °C < T
J
< 125 °C if 5 kΩ < R
CL
< 40 kΩ
Figure 11 shows the output current protection threshold versus R
CL
value in the range 5 kΩ
to 40 kΩ.
The disable time t
DISABLE
before recovering normal operation can be easily programmed by
means of the accurate thresholds of the logic inputs. It is affected whether by C
EN
and R
EN
Table 7. Truth table
Inputs Outputs
EN IN1 IN2 OUT1 OUT2
LX
(1)
1. X = Don't care
X High Z
(2)
2. High Z = High impedance output
High Z
HLLGNDGND
HHLVsGND
HLHGNDVs
HHHVsVs
11050
R
CL
----------------