Datasheet

L5987 Application information
Doc ID 14972 Rev 3 21/41
Equation 17
where:
Equation 18
Equation 19
As seen in Chapter 5.3 two different kind of network can compensate the loop. In the two
following paragraph the guidelines to select the Type II and Type III compensation network
are illustrated.
6.4.1 Type III compensation network
The methodology to stabilize the loop consists of placing two zeros to compensate the effect
of the LC double pole, so increasing phase margin; then to place one pole in the origin to
minimize the dc error on regulated output voltage; finally to place other poles far away the
zero dB frequency.
If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a
frequency higher than the desired bandwidth (that is: 2π∗ESR∗COUT<1/BW), the type III
compensation network is needed. Multi layer ceramic capacitors (MLCC) have very low ESR
(<1 mΩ), with very high frequency zero, so type III network is adopted to compensate the
loop.
In Figure 11 the type III compensation network is shown. This network introduces two zeros
(f
Z1
, f
Z2
) and three poles (f
P0
, f
P1
, f
P2
). They expression are:
Equation 20
G
LC
s()
1
s
2π f
zESR
⋅
--------------------------+
1
s
2π Qf⋅
LC
⋅
----------------------------
s
2π f
LC
⋅
-------------------
⎝⎠
⎛⎞
2
++
-------------------------------------------------------------------------=
f
LC
1
2π LC
OUT
⋅ 1
ESR
R
OUT
-------------- -+⋅⋅
------------------------------------------------------------------------= f
zESR
1
2π ESR C
OUT
⋅⋅
------------------------------------------- -=,
Q
R
OUT
LC
OUT
R
OUT
ESR+()⋅⋅ ⋅
LC
OUT
R
OUT
ESR⋅⋅+
------------------------------------------------------------------------------------------
R
OUT
V
OUT
I
OUT
--------------=,=
f
Z1
1
2π C
3
R
1
R
3
+()⋅⋅
------------------------------------------------= f
Z2
1
2π R
4
C
4
⋅⋅
------------------------------=,