L5987 3 A step-down switching regulator Features ■ 3 A DC output current ■ 2.9 V to 18 V input voltage ■ Output voltage adjustable from 0.6 V ■ 250 kHz switching frequency, programmable up to 1 MHz ■ Internal soft-start and inhibit ■ Low dropout operation: 100% duty cycle ■ Voltage feed-forward ■ Zero load current operation ■ Over current and thermal protection ■ VFQFPN3x3-8L and HSOP8 package HSOP8 exposed pad Description The L5987 is a step-down switching regulator with 3.
Contents L5987 Contents 1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Thermal data . . . . . . . .
L5987 Contents 8 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin settings L5987 1 Pin settings 1.1 Pin connection Figure 2. Pin connection (top view) OUT SYNCH GND INH FSW COMP 1.2 FB Pin description Table 1. 4/41 VCC Pin description N. Type 1 OUT Description Regulator output 2 SYNCH Master/slave synchronization. When it is left floating, a signal with a phase shift of half a period respect to the power turn on is present at the pin.
L5987 2 Maximum ratings Maximum ratings Table 2. Absolute maximum ratings Symbol Parameter Vcc Input voltage OUT Output DC voltage Value 20 -0.3 to VCC FSW, COMP, SYNCH Analog pin 3 -0.3 to 4 INH Inhibit pin -0.3 to VCC FB Feedback voltage -0.3 to 1.5 Power dissipation at VFQFPN TA < 60 °C HSOP PTOT Unit 1.5. V W 2 TJ Junction temperature range -40 to 150 °C Tstg Storage temperature range -55 to 150 °C Value Unit Thermal data Table 3.
Electrical characteristics 4 L5987 Electrical characteristics TJ = 25 °C, VCC = 12 V, unless otherwise specified. Table 4. Electrical characteristics Values Symbol Parameter Test condition Unit Min VCC Operating input voltage range (1) VCCON Turn on VCC threshold (1) VCCHYS VCC UVLO hysteresis (1) RDS(on) MOSFET on resistance ILIM 2.9 Max 18 2.9 0.175 V 0.3 140 170 140 220 3.5 4.0 4.
L5987 Electrical characteristics Table 4. Electrical characteristics (continued) Values Symbol Parameter Test condition Unit Min Typ Max Error amplifier VCH High level output voltage VFB < 0.6 V VCL Low level output voltage VFB > 0.6 V IFB Bias source current VFB = 0 V to 0.8 V 1 μA VFB = 0.5 V, VCOMP = 1 V 20 mA Sink COMP pin VFB = 0.7 V, VCOMP = 1 V 25 mA Open loop voltage gain (2) 100 dB IO SOURCE Source COMP pin IO SINK GV 3 V 0.
Functional description 5 L5987 Functional description The L5987 is based on a “voltage mode”, constant frequency control. The output voltage VOUT is sensed by the feedback pin (FB) compared to an internal reference (0.6 V) providing an error signal that, compared to a fixed frequency sawtooth, controls the on and off time of the power switch. The main internal blocks are shown in the block diagram in Figure 3.
L5987 5.1 Functional description Oscillator and synchronization Figure 4 shows the block diagram of the oscillator circuit. The internal oscillator provides a constant frequency clock. Its frequency depends on the resistor externally connect to FSW pin. In case the FSW pin is left floating the frequency is 250 kHz; it can be increased as shown in Figure 6 by external resistor connected to ground.
Functional description 10/41 L5987 Figure 5. Sawtooth: voltage and frequency feed forward; external synchronization Figure 6.
L5987 5.2 Functional description Soft-start The soft-start is essential to assure correct and safe start up of the step-down converter. It avoids inrush current surge and makes the output voltage increases monothonically. The soft-start is performed by a staircase ramp on the non-inverting input (VREF) of the error amplifier.
Functional description 5.3 L5987 Error amplifier and compensation The error amplifier (E/A) provides the error signal to be compared with the sawtooth to perform the pulse width modulation. Its non-inverting input is internally connected to a 0.6 V voltage reference, while its inverting input (FB) and output (COMP) are externally available for feedback and frequency compensation. In this device the error amplifier is a voltage mode operational amplifier so with high DC gain and low output impedance.
L5987 5.4 Functional description Overcurrent protection The L5987 implements the over-current protection sensing current flowing through the power MOSFET. Due to the noise created by the switching activity of the power MOSFET, the current sensing is disabled during the initial phase of the conduction time. This avoids an erroneous detection of a fault condition. This interval is generally known as “masking time” or “blanking time”. The masking time is about 200 ns.
Functional description Figure 8. 5.5 L5987 Over-current protection strategy Inhibit function The inhibit feature allows to put in stand-by mode the device.With INH pin higher than 1.9 V the device is disabled and the power consumption is reduced to less than 30 μA. With INH pin lower than 0.6 V, the device is enabled. If the INH pin is left floating, an internal pull up ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. The pin is also VCC compatible. 5.
L5987 5.7 Functional description Maximum DC output current L5987A (HSOP8) The L5987A can manage DC output currents up to 3 A and the rated RMS current of its internal power switch is 3 A. So the L5987A can deliver 3 A with 100% of duty cycle. 5.8 Maximum DC output current L5987 (VFQFPN) The L5987 can manage DC output currents up to 3 A. However the rated RMS current of its internal power switch is 2.5 A.
Functional description L5987 With VIN = 3.3 V, VOUT = 1.8 V, IO = 2.7 A, RDS(on) = 220 mΩ, VF = 0.35 V and DCR = 30 mΩ, the duty is D = 73%, so the maximum DC output current results 2.926 A, higher than the desired current. Figure 9. Note: 16/41 Maximum DC output current for VQFN package vs duty cycle For duty cycles lower than 69%, the RMS current does not limit the maximum DC output current of 3 A.
L5987 Application information 6 Application information 6.1 Input capacitor selection The capacitor connected to the input has to be capable to support the maximum input operating voltage and the maximum RMS input current required by the device. The input capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR, affecting the overall system efficiency.
Application information 6.2 L5987 Inductor selection The inductance value fixes the current ripple flowing through the output capacitor. So the minimum inductance value in order to have the expected current ripple has to be selected. The rule to fix the current ripple value is to have a ripple at 20%-40% of the output current.
L5987 6.3 Application information Output capacitor selection The current in the capacitor has a triangular waveform which generates a voltage ripple across it. This ripple is due to the capacitive component (charge or discharge of the output capacitor) and the resistive component (due to the voltage drop across its ESR). So the output capacitor has to be selected in order to have a voltage ripple compliant with the application requirements.
Application information 6.4 L5987 Compensation network The compensation network has to assure stability and good dynamic performance. The loop of the L5987 is based on the voltage mode control. The error amplifier is a voltage operational amplifier with high bandwidth. So selecting the compensation network the E/A will be considered as ideal, that is, its bandwidth is much larger than the system one. The transfer functions of PWM modulator and the output LC filter are studied (see Figure 11.).
L5987 Application information Equation 17 s 1 + ------------------------2π ⋅ f zESR G LC ( s ) = ------------------------------------------------------------------------2 s s 1 + ---------------------------+ ⎛⎝ -------------------⎞⎠ 2π ⋅ f LC 2π ⋅ Q ⋅ f LC where: Equation 18 1 f LC = -----------------------------------------------------------------------, ESR 2π ⋅ L ⋅ C OUT ⋅ 1 + --------------R OUT 1 f zESR = ------------------------------------------2π ⋅ ESR ⋅ C OUT Equation 19 R OUT ⋅ L ⋅ C OUT ⋅ ( R
Application information L5987 Equation 21 f P0 = 0, 1 -, f P1 = ----------------------------2π ⋅ R 3 ⋅ C 3 1 f P2 = ------------------------------------------C4 ⋅ C5 ------------------2π ⋅ R 4 ⋅ C4 + C5 Figure 11. Type III compensation network In Figure 12 the Bode diagram of the PWM and LC filter transfer function (GPW0 · GLC(f)) and the open loop gain (GLOOP(f) = GPW0 · GLC(f) · GTYPEIII(f)) are drawn. Figure 12.
L5987 Application information Equation 22 BW ⋅ K R 4 = ------------------ ⋅ R 1 f LC where K is the feed forward constant and 1/K is equals to 9. 3. Calculate C4 by placing the zero at 50% of the output filter double pole frequency (fLC): Equation 23 1 C 4 = --------------------------π ⋅ R 4 ⋅ f LC 4. Calculate C5 by placing the second pole at four times the system bandwidth (BW): Equation 24 C4 C 5 = ------------------------------------------------------------2π ⋅ R 4 ⋅ C 4 ⋅ 4 ⋅ BW – 1 5.
Application information L5987 Figure 13.
L5987 6.4.2 Application information Type II compensation network If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a frequency lower than the desired bandwidth (that is: 2π∗ESR∗COUT>1/BW), this zero helps stabilize the loop. Electrolytic capacitors show not negligible ESR (>30 mΩ), so with this kind of output capacitor the type II network combined with the zero of the ESR allows stabilizing the loop. In Figure 14 the type II network is shown. Figure 14.
Application information L5987 Figure 15. Open loop gain: module Bode diagram The guidelines for positioning the poles and the zeroes and for calculating the component values can be summarized as follow: 1. Choose a value for R1, usually between 1 kΩ and 5 kΩ, in order to have values of C4 and C5 not comparable with parasitic capacitance of the board. 2.
L5987 Application information Equation 29 C4 C 5 = ------------------------------------------------------------2π ⋅ R 4 ⋅ C 4 ⋅ 4 ⋅ BW – 1 For example with VOUT = 3.3 V, VIN = 12 V, IO = 3 A, L = 10 μH, COUT = 330 μF, ESR = 35 mΩ, the type II compensation network is: R 1 = 1.5kΩ, R 2 = 330Ω, R 4 = 10kΩ, C 4 = 47nF, C 5 = 82pF In Figure 16 is shown the module and phase of the open loop gain. The bandwidth is about 32 kHz and the phase margin is 45°.
Application information L5987 Figure 16.
L5987 6.5 Application information Thermal considerations The thermal design is important to prevent the thermal shutdown of device if junction temperature goes above 150 °C. The three different sources of losses within the device are: a) conduction losses due to the not negligible RDS(on) of the power switch; these are equal to: Equation 30 2 P ON = R DSON ⋅ ( I OUT ) ⋅ D Where D is the duty cycle of the application and the maximum RDS(on) over temperature is 220 mΩ.
Application information L5987 of heat. The RthJA measured on the demonstration board described in the following paragraph is about 60 °C/W for the VFQFPN package and about 40 °C/W for the HSOP package. Figure 17. Switching losses 6.6 Layout considerations The PC board layout of switching DC/DC regulator is very important to minimize the noise injected in high impedance nodes and interferences generated by the high switching current loops.
L5987 Application information Figure 18.
Application information 6.7 L5987 Application circuit In Figure 19 the demonstration board application circuit is shown. Figure 19. Demonstration board application circuit Vin=2.9V - 18V C1 22u 25V VCC C6 220n INH 25V GND 8 1 L5987/A 3 7 6 FSW 4 2 SYNCH 5 FB R4 2K C2 22u 25V D1 STPS2L25 R1 4.99K C4 10hF C5 330pF R2 2.49k R3 330 C3 2.2nF Component list Reference 32/41 Vout=1.8V COMP R5 150k Table 9. L1 5.
L5987 Application information Figure 20. PCB layout: L5987 and L5987A (component side) Figure 21. PCB layout: L5987 and L5987A (bottom side) Figure 22.
Application information L5987 Figure 23. Junction temperature vs output current VIN = 12 V Figure 24. Junction temperature vs output current VIN = 5 V Figure 25. Junction temperature vs output current VIN = 3.3 V Figure 26. Efficiency vs output current VIN = 12 V 92 FSW=250kHz 90 VO=5V E ffic ie n c y [% ] 88 86 VO=3.3V 84 82 VO=2.5V 80 78 VIN=12V 76 0.3 0.8 1.3 1.8 2.3 2.8 Io [A] Figure 27. Efficiency vs output current VIN = 5 V Figure 28. Efficiency vs output current VIN = 3.
L5987 Application information Figure 29. Load regulation Figure 30. Line regulation 1.2 1 VCC=12V IO=1A VCC=5V 0.8 0.8 Δ V FB/V FB [%] Δ VFB/VFB [%] 1 0.6 0.4 IO=2A IO=3A 0.6 0.4 0.2 0.2 0 0 0 0.5 1 1.5 2 2.5 2 3 4 6 8 10 12 14 16 18 VCC [V] IO [A] Figure 31. Load transient: from 0.4 A to 3 A Figure 32. Soft-start IL 1A/div VOUT 100mV/div AC coupled VOUT 0.5V/div 1V/div COUT=47uF L=3.8uH FSW=520k IL 1A/div Time base 1ms/div Time base 100us/div Figure 33.
Package mechanical data 7 L5987 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
L5987 Package mechanical data Table 10. VFQFPN8 (3 x 3 x 1.08 mm) mechanical data mm inch Dim. Min Typ Max Min Typ Max 0.80 0.90 1.00 0.0315 0.0354 0.0394 A1 0.02 0.05 0.0008 0.0020 A2 0.70 0.0276 A3 0.20 0.0079 A b 0.18 0.23 0.30 0.0071 0.0091 0.0118 D 2.95 3.00 3.05 0.1161 0.1181 0.1200 D2 2.23 2.38 2.48 0.0878 0.0937 0.0976 E 2.95 3.00 3.05 0.1161 0.1181 0.1200 E2 1.65 1.70 1.75 0.0649 0.0669 0.0689 e L 0.50 0.35 0.40 ddd 0.0197 0.45 0.
Package mechanical data Table 11. L5987 HSOP8 mechanical data mm inch Dim Min Typ A Max Typ 1.70 Max 0.0669 A1 0.00 A2 1.25 b 0.31 0.51 0.0122 0.0201 c 0.17 0.25 0.0067 0.0098 D 4.80 4.90 5.00 0.1890 E 5.80 6.00 6.20 0.2283 0.2441 E1 3.80 3.90 4.00 0.1496 0.1575 e 0.15 0.00 0.0059 0.0492 0.1929 0.1969 1.27 h 0.25 0.50 0.0098 0.0197 L 0.40 1.27 0.0157 0.0500 k 0 8 0.3150 0.10 0.0039 ccc Figure 35.
L5987 8 Order codes Order codes Table 12.
Revision history 9 L5987 Revision history Table 13.
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