Datasheet

Block diagram and pins description L5150GJ
6/29 Doc ID 15540 Rev. 12
Table 2. Pins description
Pin Name Function
1R
es_Adj
Reset adjustable threshold. Connected to an appropriate external
voltage divider, it allows to properly set the reset threshold down
to 3.5 V. Connect to GND if not needed.
2R
es
Reset output. Internally connected to Vo through a 20 KΩ pull-up
resistor. This pin is pulled low when V
o
<V
o_th
. Keep open if not
needed.
3V
cr
Reset delay. Connect an external capacitor between V
cr
pin and
ground to adjust the reset delay time. Keep open if not needed.
4 GND Ground reference.
5 NC Not connected.
6V
o
5 V regulated output. Block to GND with a ceramic capacitor
(C
o
≥ 220 nF for regulator stability).
7V
S
Supply voltage, block directly to GND on the IC with a capacitor.
8 NC Not connected.
9E
n
Enable input. A high signal switches the regulator on. Connect to
V
S
if not needed.
10 EW
i
Early warning input. This pin monitors the V
S
voltage level through
a resistor divider. Connect to V
S
if not needed.
11 NC Not connected.
12 EW
o
Early warning output. Internally connected to V
o
through 20 KΩ
pull up resistor. This pin is pulled low when EW
i
is below bandgap
reference voltage. Keep open if not needed.
-TAB
TAB is connected to the substrate of the chip: connect to GND or
leave open (see Figure 2).