Datasheet

Block diagram and pins description L5150CJ / L5150CS
6/34 Doc ID 15542 Rev. 15
Table 2. Pins description
Pin name
PowerSSO-12
pin #
SO-8
pin #
Function
R
es_Adj
18
Reset adjustable threshold. Connected to an
appropriate external voltage divider, it allows to
properly set the reset threshold down to 3.5 V.
Connect to GND if not needed.
R
es
21
Reset output. Internally connected to V
o
through a
20 KΩ pull up resistor. This pin is pulled low when
V
o
<V
o_th
. Keep open if not needed.
V
cr
32
Reset delay. Connect an external capacitor between
V
cr
pin and ground to adjust the reset delay time.
Keep open if not needed.
GND 4 3 Ground reference.
NC 5, 11, 8, 9 - Not connected.
V
o
64
5 V regulated output. Block to GND with a ceramic
capacitor (C
o
≥ 220 nF for regulator stability).
V
S
75
Supply voltage, block directly to GND on the IC with a
capacitor.
EW
i
10 6
Early warning input. This pin monitors the V
S
voltage
level through a resistor divider. Connect to V
S
if not
needed.
EW
o
12 7
Early warning output. Internally connected to V
o
through 20 KΩ pull up resistor. This pin is pulled low
when EW
i
is below bandgap reference voltage. Keep
open if not needed.
TAB - -
TAB is connected to the substrate of the chip: connect
toGND or leave open (see Figure 2 for PowerSSO-12
only).