Datasheet

L4995 Application information
Doc ID 13103 Rev 14 19/35
Reset is active when E
n
is high.
Figure 29. Reset timing diagram
3.3 Watchdog
A connected microcontroller is monitored by the watchdog input W
i
. If pulses are missing,
the Reset output pin is set to low. The pulse sequence time can be set within a wide range
with the external capacitor, C
tw
. The watchdog circuit discharges the capacitor C
tw
, with the
constant current Icwd. If the lower threshold V
wlth
is reached, a watchdog reset is generated.
To prevent this the microcontroller must generate a positive edge during the discharge of the
capacitor before the voltage has reached the threshold V
wlth
. In order to calculate the
minimum time t, during which the micro-controller must output the positive edge, the
following equation can be used:
Equation 3
(V
whth
-V
wlth
) x C
tw
= I
cwd
x t
Every W
i
positive edge switches the current source from discharging to charging. The same
happens when the lower threshold is reached. When the voltage reaches the upper
threshold, V
whth
, the current switches from charging to discharging. The result is a saw-tooth
voltage at the watchdog timer capacitor C
tw
.
Figure 30. Watchdog timing diagram
trr
<
trr
trd
Tosc
Vrhth
Vrlth
Res
Vcr
Vo
Wi
Vout_th
trr
<
trr
trd
Tosc
Vrhth
Vrlth
Res
Vcr
Vo
Wi
Vout_th
GAPGMS00077
:
L
9
FZ
5
HV
9
ZKWK
9
ZOWK
7
ZRS
7
ZRO
:
L
9
FZ
5
HV
9
ZKWK
9
ZOWK
7
ZRS
7
ZRO
'!0'-3