Datasheet
Application information L4993
18/32 Doc ID 13517 Rev 8
Figure 26. Reset timing diagram
3.3 Watchdog
A connected microcontroller is monitored by the watchdog input Wi. If pulses are missing,
the Reset output pin is set to low. The pulse sequence time can be set within a wide range
with the external capacitor, Ctw. The watchdog circuit discharges the capacitor Ctw, with the
constant current Icwd. If the lower threshold Vwlth is reached, a watchdog reset is
generated. To prevent this the microcontroller must generate a positive edge during the
discharge of the capacitor before the voltage has reached the threshold Vwlth. In order to
calculate the minimum time t, during which the micro-controller must output the positive
edge, the following equation can be used:
(Vwhth-Vwlth) x Ctw = Icwd x t
Every Wi positive edge switches the current source from discharging to charging. The same
happens when the lower threshold is reached. When the voltage reaches the upper
threshold, Vwhth, the current switches from charging to discharging. The result is a
saw-tooth voltage at the watchdog timer capacitor Ctw.
Figure 27. Watchdog timing diagram
TRR
TRR
TRD4 OSC
4OSC
6RHTH
6RLTH
2ES
6CR
6O
7I
6OUT?TH
'!0'#&4
2ES
6CW
7I
6W
LTH
6WHTH
TWOL
4WO P
'!0'2)
6WLTH