L6563S Enhanced transition-mode PFC controller Features ■ Tracking boost function ■ Fast “bidirectional” input voltage feedforward (1/V2 correction) ■ Interface for cascaded converter's PWM controller ■ Remote ON/OFF control ■ Accurate adjustable output overvoltage protection ■ Protection against feedback loop disconnection (latched shutdown) ■ Inductor saturation protection ■ Low (≤ 100 µA) start-up current ■ 6 mA max.
Contents L6563S Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Pin connection . . . . . . . . . .
L6563S List of table List of table Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of figure L6563S List of figure Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43.
L6563S Figure 49. Figure 50. Figure 51. load Figure 52. W load Figure 53. Figure 54. Figure 55. matic Figure 56. List of figure L6563S 100 W TM PFC demonstration board: compliance to EN61000-3-2 standard . . . 36 L6563S 100 W TM PFC demonstration board: compliance to JEITA-MITI standard . . . . . 36 L6563S 100 W TM PFC demonstration board: input current waveform @230-50 Hz - 100 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description 1 L6563S Description The L6563S is a current-mode PFC controller operating in transition mode (TM). Coming with the same pin-out as its predecessor L6563, it offers improved performance and additional functions. The highly linear multiplier, along with a special correction circuit that reduces crossover distortion of the mains current, allows wide-range-mains operation with an extremely low THD even over a large load range.
L6563S Maximum ratings 2 Maximum ratings 2.1 Absolute maximum ratings Table 1. Symbol Pin Vcc 14 --- 1, 3, 7 --- 2.2 Absolute maximum ratings Parameter Value Unit IC supply voltage (Icc = 20 mA) self-limited V Max. pin voltage (Ipin =1 mA) Self-limited V -0.3 to 8 V -0.3 to Vcc V 3 mA -10 (source) 10 (sink) mA +/- 1250 V +/- 2000 V Value Unit 2, 4 to 6, 8, 10 Analog inputs and outputs VPWM_STOP 9 Analog output IPWM_STOP 9 Max.
Pin connection 3 L6563S Pin connection Figure 2. Pin connection ,19 9FF &203 *' 08/7 *1' &6 =&' 9)) 581 7%2 3:0B6723 3)&B2. 3:0B/$7&+ !- V Table 3. n° Pin description Name Function INV Inverting input of the error amplifier. The information on the output voltage of the PFC preregulator is fed into the pin through a resistor divider.
L6563S Pin connection Table 3. n° 7 Pin description (continued) Name Function PFC_OK PFC pre-regulator output voltage monitoring/disable function. This pin senses the output voltage of the PFC pre-regulator through a resistor divider and is used for protection purposes. If the voltage on the pin exceeds 2.5 V the IC stops switching and restarts as the voltage on the pin falls below 2.4 V. However, if at the same time the voltage of the INV pin falls below 1.66V, a feedback failure is assumed.
Pin connection L6563S Figure 3. Typical system block diagram 0&# 02% 2%'5,!4/2 $# $# #/.6%24%2 6OUTDC 6INAC 07- IS TURNED OFF IN CASE OF 0&#gS ANOMALOUS OPERATION FOR SAFETY , ( , 3 07- OR 2ESONANT #/.
L6563S 4 Electrical characteristics Electrical characteristics TJ = -25 to 125 °C, VCC = 12 V, CO = 1 nF between pin GD and GND, CFF = 1 µF and RFF = 1 MΩ between pin VFF and GND; unless otherwise specified. Table 4. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max.
Electrical characteristics Table 4. Electrical characteristics (continued) Symbol Parameter Gv Voltage gain GB Gain-bandwidth product ICOMP VCOMP L6563S Test condition Open loop Min. Typ. Max. Unit 60 80 dB 1 MHz Source current VCOMP = 4 V, VINV = 2.4 V 2 4 mA Sink current VCOMP = 4 V, VINV = 2.6 V 2.5 4.5 mA Upper clamp voltage ISOURCE = 0.5 mA 5.7 6.2 6.7 Burst-mode voltage (3) 2.3 2.4 2.5 2.1 2.25 2.4 Lower clamp voltage ISINK = 0.
L6563S Electrical characteristics Electrical characteristics (continued) Table 4. Symbol Parameter VZCDT Triggering voltage (negative-going edge) IZCDb Input bias current Test condition Min. Typ. Max. Unit 0.5 0.7 VZCD = 1 to 4.5 V 0.9 V 1 µA IZCDsrc Source current capability -2.5 -4 mA IZCDsnk Sink current capability 2.5 5 mA Tracking boost function ΔV ITBO Dropout voltage VVFF-VTBO Linear operation -20 20 mV 0 0.2 mA IINV-ITBO current mismatch ITBO = 25 µA to 0.2mA -5.
Electrical characteristics Table 4. Electrical characteristics (continued) Symbol VVFF L6563S Parameter Test condition Linear operation range Min. Typ. Max. Unit 0.8 3 V -1 µA PWM_LATCH Ileak Low level leakage current VPWM_LATCH = 0 VH High level IPWM_LATCH = -0.5 mA 4.5 V VH High level IPWM_LATCH = -0.25 mA Vcc = VccOff 2.5 V VH High level IPWM_LATCH = -0.25 mA Vcc = VccOff TJ = 25 °C 2.
L6563S Typical electrical performance 5 Typical electrical performance Figure 4. IC consumption vs VCC Figure 5. 100 IC consumption vs TJ 10 Operating 10 Quiescent Disabled or during OV P 1 Co=1nF f =70kHz Tj = 25°C I cc [m A] VCC=12V Co = 1nF f =70kHz I c current (m A) 1 0.1 Latched off 0.1 Before Start up 0.01 VccOFF VccON 0.01 0. 001 0 5 10 15 20 25 -50 30 -25 0 25 50 Figure 6. 75 100 125 150 175 Tj (C) Vcc [V ] Vcc Zener voltage vs TJ Figure 7.
Typical electrical performance Figure 8. L6563S Feedback reference vs TJ Figure 9. 2. 6 E/A output clamp levels vs TJ 7 Uper Clam p 6 VCC = 12V 2.55 5 V COM P (V ) pi n INV (V ) V CC = 12V 2. 5 4 3 Lower Clamp 2 2.45 1 0 2. 4 -50 -25 0 25 50 75 Tj (C) 100 125 150 -50 175 -25 0 25 50 75 100 Figure 10. UVLO saturation vs TJ 150 175 Figure 11. OVP levels vs TJ 2. 5 1 0.9 2. 48 VCC = 0V 0.8 OV P T h 2. 46 P FC_OK l evels (V ) 0.7 0.6 V 125 Tj (C) 0.5 0.4 2. 44 2.
L6563S Typical electrical performance Figure 12. Inductor saturation threshold vs TJ Figure 13. Vcs clamp vs TJ 1.9 1. 4 1.8 1.7 1. 3 VCSx (V ) CS pi n (V ) 1.6 1.5 VCC = 12V VCOMP =Upper clamp 1. 2 1.4 1.3 1. 1 1.2 1.1 1 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 Figure 14. ZCD sink/source capability vs TJ 100 125 150 175 Figure 15.
Typical electrical performance L6563S Figure 16. TBO clamp vs TJ Figure 17. VVFF - VTBO dropout vs TJ 5 3.5 4 3 3.25 2 mV 1 V 3 0 -1 -2 2.75 -3 -4 -5 2.5 -50 -25 0 25 50 Tj (C) 75 100 125 150 -50 175 Figure 18. IINV - ITBO current mismatch vs TJ -25 0 25 50 75 100 125 150 175 T j (C) Figure 19. IINV - ITBO mismatch vs ITBO current 0 -1.6 VCC = 12V -1.8 -1 100*{I(I NV )-I(TBO)}/I (TBO) [ % ] 100*{I(INV)-I(TBO)}/I(TBO) [ % ] -0.5 I TBO = 200uA -1.
L6563S Typical electrical performance Figure 20. R discharge vs TJ Figure 21. Line drop detection threshold vs TJ 20 90 18 80 16 70 14 60 50 mV kOhm 12 10 40 8 30 6 20 4 10 2 0 0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 Figure 22. VMULTpk - VVFF dropout vs TJ 100 125 150 175 150 175 Figure 23. PFC_OK threshold vs TJ 2 0.4 1. 5 0.35 1 0.3 0. 5 0.25 Th (V ) ⎯ (m V) 75 Tj (C) Tj (C) 0 ON 0.2 -0. 5 0.15 -1 0.1 -1. 5 0.
Typical electrical performance L6563S Figure 24. PFC_OK FFD threshold vs TJ Figure 25. PWM_LATCH high saturation vs TJ 2 10 VCC = 12V 1.9 9 1.7 7 1.6 6 1.5 5 1.4 -50 Isource =500uA 8 V VFFD Th (V ) 1.8 -25 0 25 50 75 100 125 150 Isource =250uA 4 17 5 -50 -25 0 25 Tj(C) Figure 26. RUN threshold vs TJ 50 75 T j (C) 100 125 150 175 Figure 27. PWM_STOP low saturation vs TJ 0. 25 1 ON 0.2 VCC = 12V Isink = 0. 5m A 0.8 OFF V V 0. 15 VCC = 12V 0.1 0.6 0. 05 0.
L6563S Typical electrical performance Figure 28. Multiplier characteristics @ VFF = 1 V Figure 29. Multiplier characteristics @ VFF = 3 V 700 1. 2 VCOMP 1. 1 V COM P Upper voltage cl amp 1 600 Upper vo ltage 5 .5 5 .0V 0. 9 4.5 V 500 4. 0V 400 0. 8 V CS (V ) V CS (m V) 5. 5V 0. 7 0. 6 0. 5 5. 0V 4. 5V 300 3.5 V 4. 0V 0. 4 200 0. 3 3. 5V 0. 2 3.0 100 3. 0V 0. 1 2. 6V 2.6 V 0 0 0 0. 1 0.2 0. 3 0. 4 0.5 0.6 0.7 0. 8 0.9 1 1.1 0 0. 5 1 1.
Typical electrical performance L6563S Figure 32. Gate drive output saturation vs TJ Figure 33. Delay to output vs TJ 12 300 High level 10 250 TD(H-L) (n s) V 8 6 200 VCC = 12V 150 4 100 Low level 2 50 0 -50 -25 0 25 50 75 100 125 150 175 -50 Tj (C) Figure 34.
L6563S Application information 6 Application information 6.1 Overvoltage protection Normally, the voltage control loop keeps the output voltage Vo of the PFC pre-regulator close to its nominal value, set by the ratio of the resistors R1 and R2 of the output divider. A pin of the device (PFC_OK) has been dedicated to monitor the output voltage with a separate resistor divider (R3 high, R4 low, see Figure 35). This divider is selected so that the voltage at the pin reaches 2.
Application information 6.2 L6563S Feedback failure protection (FFP) The OVP function above described handles “normal” over voltage conditions, i.e. those resulting from an abrupt load/line change or occurring at start-up. In case the overvoltage is generated by a feedback disconnection, for instance when the upper resistor of the output divider (R1) fails open, an additional comparator detects the voltage at pin INV. If the voltage is lower than 1.
L6563S Application information Figure 36.
Application information L6563S The twice-mains-frequency (2•fL) ripple appearing across CFF is triangular with a peak-topeak amplitude that, with good approximation, is given by: ΔVFF = 2 VMULTpk 1 + 4fLRFF CFF where fL is the line frequency.
L6563S 6.4 Application information THD optimizer circuit The L6563S is provided with a special circuit that reduces the conduction dead-angle occurring to the AC input current near the zero-crossings of the line voltage (crossover distortion). In this way the THD (total harmonic distortion) of the current is considerably reduced. A major cause of this distortion is the inability of the system to transfer energy effectively when the instantaneous line voltage is very low.
Application information L6563S Figure 39. THD optimization: standard TM PFC controller (left side) and L6563S (right side) Input current Input current Rectified mains voltage Rectified mains voltage Imains Input current Imains Input current Vdrain MOSFET's drain voltage Vdrain MOSFET's drain voltage Essentially, the circuit artificially increases the ON-time of the power switch with a positive offset added to the output of the multiplier in the proximity of the line voltage zero-crossings.
L6563S Application information V(TBO)/RT, that is internally 1:1 mirrored and sunk from pin INV (#1) input of the L6563S's error amplifier. In this way, when the mains voltage increases the voltage at TBO pin will increase as well and so will do the current flowing through the resistor connected between TBO and GND. Then a larger current will be sunk by INV pin and the output voltage of the PFC pre-regulator will be forced to get higher.
Application information L6563S Figure 40. Tracking boost block 42!#+).' "//34 #522%.4 -)22/2 4"/ )4"/ #/-0 "5&&%2 )4"/ FROM 6&& 6 TO -ULTIPLIER 24 ).6 6 %RROR !MPLIFIER 6/54 2 2 !- V Figure 41. Tracking output voltage vs Input voltage characteristic with TBO 9R 9R [ 9R 9LQ 9R 9LQ 9LQ 9LQ 9LQ [ !- V 6.
L6563S Application information occasionally slightly saturate when the PFC stage is restarted because of a larger load demand. This happens when the restart occurs at an unfavorable line voltage phase, i.e. when the output voltage is significantly below the rectified peak voltage. As a result, in the boost inductor the inrush current coming from the bridge rectifier adds up to the switched current and, furthermore, there is little or no voltage available for demagnetization.
Application information L6563S Figure 43. Interface circuits that let dc-dc converter's controller IC drive L6563S in burst mode 3)&B2. / $ / + / 6 3)&B6723 581 3)&B2. / / + / 6 3)&B6723 581 !- V The third communication line is the pin PWM_STOP (#9), which works in conjunction with the pin RUN (#10). The purpose of the PWM_STOP pin is to inhibit the PWM activity of both the PFC stage and the cascaded dc-dc converter.
L6563S Application information Figure 45.
Application information L6563S In table 1 it is possible to find a summary of all of the above mentioned working conditions that cause the device to stop operating. Figure 47. Brownout protection (master PFC) Table 5. Summary of L6563S idle states Typical IC PWM_LATCH PWM_STOP Condition Caused or revealed bey IC behavior Restart condition consumption Status Status UVLO Vcc < VccOff Disabled Vcc > VccOn 90 µA Off High Feedback disconnected PFC_OK > VPFC_OK_S AND INV < 1.
L6563S Application examples and ideas 7 Application examples and ideas Figure 48. Demonstration board EVL6563S-100W, wide-range mains: electrical schematic ' 1 a / 65: 34 ;;;9 ' *%8 - / +) < 5 7 ) )8 6( $ - 0.'6 & 1 B a 9DF & 1 9 & 1 5 17& 5 6 ' 677+ / & 1 5 5 & X) 9 ' // - 0.'6 5 0 5 0 ' %=; & 5 0 5 . 5 0 5 .
Application examples and ideas L6563S Figure 49. L6563S 100 W TM PFC demonstration board: compliance to EN61000-3-2 standard Meas ured value Figure 50. L6563S 100 W TM PFC demonstration board: compliance to JEITA-MITI standard EN61000-3- 2 class- D lim its Measur ed value JEITA-MITI Class-Dlim its 10 Harmonic Current [A] Harmonic Current [A] 1 0.1 0.01 0.001 1 0.1 0.01 0.001 0.0001 0.
L6563S Application examples and ideas Figure 53. EVL6563S-250W TM PFC demonstration board: electrical schematic D2 1N5406 D1 D10XB60H L1 2 ~ 1 J1 2 1 90-264Vac 3 1 5 7 8 C6 10N J2 D3 STTH5L06 C5 100uF - 450V D4 LL4148 R2 47R D5 BZX55-C18 R5 150K +400Vout R3 1M0 JPX2 +400Vdc +400Vdc NC RTN RTN 1 2 3 4 5 JPX6 RX3 47R LH30-792Y3R0-01 C2 1uF-X2 Z1 R4 2M2 C4 1.5uF-520V _ ~ 3 4 C1 470N-X2 R1 NTC 1R0-S237 L2 180uH + F1 FUSE 4A R6 1M0 JPX7 R7 1M0 PCB REV.
MKDS 1,5/3-5.08 CN1 Doc ID 16116 Rev 4 10n C4 HT 6.
L6563S 8 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Table 6. SO14 mechanical data mm. Dim. Min Typ Max A 1.350 1.750 A1 0.100 0.250 A2 1.100 1.650 B 0.330 0.510 C 0.190 0.250 D 8.550 8.750 E 3.
Package mechanical data L6563S Figure 56.
L6563S 9 Ordering codes Ordering codes Table 7.
Revision history 10 L6563S Revision history Table 8. 42/43 Document revision history Date Revision Changes 12-Aug-2009 1 Initial release. 03-Sep-2009 2 Updated mechanical data. 29-Jan-2010 3 Updated Table 4 on page 11. 21-Dec-2010 4 Updated Figure 1 on page 1, Figure 24 on page 20, Table 3 on page 8, Table 4 on page 11, Table 5 on page 34 and Section 6.2 on page 24.
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