AN3119 Application note 250 W transition-mode PFC pre-regulator with the new L6563S Introduction This application note describes a demonstration board based on the new transition-mode PFC controller L6563S and presents the results of its bench evaluation. The board implements a 250 W, wide-range mains input PFC pre-conditioner suitable for desktop PCs, industrial SMPS, flat screen displays, and all SMPS having to meet the IEC61000-3-2 or the JEITA-MITI standard. Figure 1.
Contents AN3119 Contents 1 Main characteristics and circuit description . . . . . . . . . . . . . . . . . . . . . 4 2 Electrical diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 Test results and significant waveforms . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 Harmonic content measurement . . . . . . . . . . . . . . . . . . . .
AN3119 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43.
Main characteristics and circuit description 1 AN3119 Main characteristics and circuit description The main characteristics of the SMPS are: ● Line voltage range: 90 to 265 Vac ● Line frequency (fL): 47 to 63 Hz ● Regulated output voltage: 400 V ● Rated output power: 250 W ● Maximum 2fL output voltage ripple: 20 V pk-pk ● Hold-up time: 10 ms (VDROP after hold-up time: 300 V) ● Minimum switching frequency: 40 kHz ● Minimum estimated efficiency: 93 % (@Vin=90 Vac, Pout=250 W) ● Maximum amb
AN3119 Main characteristics and circuit description the mains voltage. Additionally, pin #10 (RUN) is connected to pin# 5 (VFF) through the R27 and R28 resistor divider, providing a voltage level for brown-out (AC mains under voltage) protection. A voltage on the RUN pin below 0.8 V shuts down (not latched) the IC and brings its consumption to a considerably lower level. The L6563S restarts as the voltage at the pin rises above 0.88 V.
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AN3119 Bill of material 3 Bill of material Table 1. EVL6563S-250W TM PFC demonstration board BOM Part type/ Case style part value /package C1 470N-X2 C10 Des. Description Supplier 6X26.
Bill of material Table 1. Des. AN3119 EVL6563S-250W TM PFC demonstration board BOM (continued) Part type/ Case style part value /package Description Supplier JPX4 Wire jumper Wire jumper JPX5 Wire jumper Insulated wire jumper JPX6 Wire jumper Wire jumper JPX7 Wire jumper Insulated wire jumper JPX8 Wire jumper Wire jumper L1 LH30-792Y3R0-01 DWG Input Emi filter - 7.
AN3119 Table 1. Bill of material EVL6563S-250W TM PFC demonstration board BOM (continued) Part type/ Case style part value /package R32 100 Ω R33 Des. Description Supplier 0805 SMD STD film res - 1/8 W - 5 % - 250 ppm/°C VISHAY 51 kΩ 0805 SMD STD film res - 1/8 W - 1 % - 100 ppm/°C VISHAY R4 2.
Test results and significant waveforms AN3119 4 Test results and significant waveforms 4.1 Harmonic content measurement One of the main purposes of a PFC pre-conditioner is the correction of input current distortion, decreasing the harmonic contents below the limits of the relevant regulations. Therefore, this demonstration board has been tested according to the European standard EN61000-3-2 class-D and Japanese standard JEITA-MITI class-D, at full load, at both the nominal input voltage mains.
AN3119 Test results and significant waveforms For user reference, waveforms of the input current and output voltage at 230 Vac and 100 Vac input voltage mains during nominal and 70 W load operation are shown in Figure 7, 8, 9, and 10. Figure 7. EVL6563S-250W TM PFC: input current waveform @230 V-50 Hz 250 W load Figure 8. CH1: Vout CH1: Vout CH2: V bridge CH2: V bridge CH4: I_AC CH4: I_AC Figure 9.
Test results and significant waveforms AN3119 load range during operation at low mains. THD increases and PF decreases during European mains operation at light load because the circuit begins working in burst mode to maintain good efficiency, preventing from operating at a too high switching frequency. In a case where the burst mode operation cannot be accepted a compromise with efficiency must be found.
AN3119 Test results and significant waveforms Figure 15. EVL6563S-250W TM PFC: static Vout regulation vs. output power 2XWSXW 9ROWDJH YV 2XWSXW 3RZHU 9RXW >9GF@ 9RXW # 9DF +] 9RXW # 9DF +] 9RXW # 9DF +] 3RXW : 3RXW : 3RXW : 3RXW : 2XWSXW 3RZHU !- V The measured output voltage at different line and static load conditions is shown in Figure 15.
Test results and significant waveforms AN3119 filtering needs. In fact, a large capacitance introduces a conduction dead-angle of the AC input current in itself, therefore reducing the effectiveness of the optimizer circuit. Figure 16. EVL6563S-250W TM PFC: MOSFET Figure 17.
AN3119 4.3 Test results and significant waveforms Voltage feed-forward and brown-out function The power stage gain of PFC pre-regulators varies with the square of the RMS input voltage. As does the crossover frequency fc of the overall open-loop gain because the gain has a single pole characteristic. This leads to large trade-offs in the design. For example, setting the gain of the error amplifier to get fc = 20 Hz @ 264 Vac means having fc = 4 Hz @ 88 Vac, resulting in sluggish control dynamics.
Test results and significant waveforms AN3119 voltage has a significant deviation from the nominal value. The circuit has the same behavior in the case of mains surge at any input voltage, and it is not affected even if the input mains surge happens at any point of the input sinewave. Figure 20. L6562A input mains surge 90 Vac to Figure 21.
AN3119 Test results and significant waveforms It is also possible to see, comparing Figure 24 and Figure 25, that the input current of the latter has a better shape and the 3rd harmonic current distortion is not noticeable; this demonstrates the benefits of the new voltage feed-forward circuit integrated into the L6563S, allowing a fast response to mains disturbances but using a quite long VFF time constant, also providing very low THD and high PF at the same time, as confirmed by the measurements below in
Test results and significant waveforms AN3119 Figure 26. EVL6563S-250W TM PFC: startup attempt at 80 Vac-60 Hz - full load CH1: PFC output voltage CH2: Vcc voltage (pin #14) CH3: RUN (pin #10) CH4: gate drive (pin #13) In Figure 26 a startup tentative below the threshold is shown. As seen, at startup the RUN pin does not allow the PFC startup even if the Vcc has reached the turn-on threshold. PFC output voltage remains at the peak of the input sinewave.
AN3119 4.4 Test results and significant waveforms Startup operation Figure 29 and 30 show the waveforms during the startup of the circuit at mains plug-in. The R5 and R11 startup resistors charge the Vcc C9 capacitor, therefore Vcc voltage rises up to the turn-on threshold, and the L6563S starts operating. For a short time the energy is supplied by the Vcc capacitor, and then the auxiliary winding with the charge pump circuit takes over.
Test results and significant waveforms 4.5 AN3119 PFC_OK pin and feedback failure (open-loop) protection During normal operation, the voltage control loop provides for the output voltage (Vout) of the PFC pre-regulator close to its nominal value, set by the resistors ratio of the feedback output divider. In the L6563S the PFC_OK pin (#7) has been dedicated to monitoring the output voltage with a separate resistor divider made up of R21, R25, R26 (high) and R33 (low), see Figure 2.
AN3119 Test results and significant waveforms Figure 31. EVL6563S-250W load transient at 115 Vac - 60 Hz - full load to no-load CH1: PFC output voltage, CH2: PFC_OK (pin #7), CH3: gate drive (pin #13), CH4: Iout The event of an open-loop is demonstrated in Figure 32 and 33; notice the protection intervention, latching the operation of the L6563S. As mentioned previously, to restart the system it is necessary to recycle the input power.
Test results and significant waveforms 4.6 AN3119 TBO (tracking boost option) To achieve the TBO function on the L6563S a dedicated input of the multiplier is available on pin #6 (TBO); the function can be realized by simply connecting a resistor (RT) between the TBO pin and ground.
AN3119 4.7 Test results and significant waveforms Power management and housekeeping functions A special feature of the L6563S is that it facilitates the implementation of the “housekeeping” circuitry needed to coordinate the operation of the PFC stage to that of the cascaded DCDC converter. The functions realized by the housekeeping circuitry ensure that transient conditions like power-up or power-down sequencing or failures of either power stage be properly handled.
Test results and significant waveforms AN3119 (#9), which is an open collector type, if it needs a pull-up resistor please connect it close to the cascaded PWM for a better noise immunity. Figure 35. Interface circuits that let the L6563S Figure 36. Interface circuits that let the L6563S switch on or off a PWM controller switch on or off a PWM controller not latched latched /. /&& 25.
AN3119 5 Layout hints Layout hints The layout of any converter is a very important phase in the design process needing as much attention by the design engineers as any other design phase. Even if it the layout phase can sometimes look time consuming a good layout surely saves time during the functional debugging and the qualification phases. Additionally, a power supply circuit with a correct layout needs smaller EMI filters or less filter stages and so it allows a consistent money saving.
Thermal map 6 AN3119 Thermal map In order to check the design reliability, a thermal mapping by means of an IR camera was done. In Figure 38 the thermal measurements of the board, component side at nominal input voltage, are shown. Some pointers visible in the image have been placed across key components or components showing high temperature. The ambient temperature during both measurements was 27 °C. It is possible to see that the PFC part has a different temperature depending on the input mains.
AN3119 Thermal map Table 2.
EMI filtering and conducted EMI pre-compliance measurements 7 AN3119 EMI filtering and conducted EMI pre-compliance measurements Figures 40, 41, 42, and 43 show the measurement in average mode of the conducted noise at full load and nominal mains voltages for both mains lines. The limits shown in the diagrams are EN55022 class-B which is the most popular standard for domestic equipment using a two-wire mains connection.
AN3119 EMI filtering and conducted EMI pre-compliance measurements Figure 43. EVL6563S-250W CE AVG Figure 42.
References 8 30/32 AN3119 References 1. L6563S datasheet 2.
AN3119 9 Revision history Revision history Table 3. Document revision history Date Revision Changes 29-Jun-2010 1 Initial release. 24-Nov-2010 2 Update Chapter 1 on page 4, Chapter 4.5 on page 20.
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