L6563H High voltage start-up transition-mode PFC Features ■ On-board 700 V start-up source ■ Tracking boost function ■ Fast “bidirectional” input voltage feedforward (1/V2 correction) ■ Interface for cascaded converter's PWM controller ■ Remote ON/OFF control ■ Accurate adjustable output overvoltage protection ■ Protection against feedback loop disconnection (latched shutdown) ■ Inductor saturation protection ■ Low (≤ 100 µA) start-up current ■ 6 mA max.
Contents L6563H Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Pin connection . . . . . . . . . .
L6563H List of table List of table Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of figure L6563H List of figure Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43.
L6563H Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. load Figure 60. Figure 61. matic Figure 62. Figure 63. Figure 64. List of figure Interface circuits for actual power-up sequencing (master PFC) . . . . . . . . . . . . . . . . . . . . 34 Brownout protection (master PFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 High-voltage start-up generator: internal schematic . . . . . . . . . . .
Description 1 L6563H Description The L6563H is a current-mode PFC controller operating in transition mode (TM) which embeds the same features existing in the L6563S with the addition of a high voltage start-up source. These functions make the IC especially suitable for applications that have to be compliant with energy saving regulations and where the PFC pre-regulator works as the master stage.
L6563H Maximum ratings 2 Maximum ratings 2.1 Absolute maximum ratings Table 1. Symbol Pin VHVS 9 IHVS Vcc ----- 2.2 Absolute maximum ratings Value Unit Voltage range (referred to ground) -0.3 to 700 V 9 Output current Self-limited IHVS 16 IC supply voltage (Icc = 20 mA) self-limited V Max. pin voltage (Ipin =1 mA) Self-limited V -0.3 to 8 V 3 mA 1, 3, 7 Parameter 2, 4 to 6, 8, 11, 12 Analog inputs and outputs IPWM_STOP 11 Max.
Pin connection 3 L6563H Pin connection Figure 2. Pin connection ).6 6CC #/-0 '$ -5,4 '.$ #3 :#$ 6&& 25. 4"/ 07-?34/0 0&#?/+ . # 07-?,!4#( (63 !- V Table 3. n° Pin description Name Function INV Inverting input of the error amplifier. The information on the output voltage of the PFC preregulator is fed into the pin through a resistor divider.
L6563H Pin connection Table 3. n° 7 Pin description (continued) Name Function PFC_OK PFC pre-regulator output voltage monitoring/disable function. This pin senses the output voltage of the PFC pre-regulator through a resistor divider and is used for protection purposes. If the voltage on the pin exceeds 2.5 V the IC stops switching and restarts as the voltage on the pin falls below 2.4 V. However, if at the same time the voltage of the INV pin falls below 1.66V, a feedback failure is assumed.
Pin connection L6563H Figure 3. Typical system block diagram 0&# 02% 2%'5,!4/2 $# $# #/.6%24%2 6OUTDC 6INAC 07- IS TURNED OFF IN CASE OF 0&#gS ANOMALOUS OPERATION FOR SAFETY , ( 07- OR 2ESONANT #/.
L6563H 4 Electrical characteristics Electrical characteristics TJ = -25 to 125 °C, VCC = 12 V, CO = 1 nF between pin GD and GND, CFF = 1 µF and RFF = 1 MΩ between pin VFF and GND; unless otherwise specified Table 4. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max.
Electrical characteristics Table 4. Electrical characteristics (continued) Symbol ΔVcs ΔVMULT KM L6563H Parameter Test condition Min. Typ. Max. Unit Output max. slope VMULT =0 to 0.4 V, VVFF = 0.8 V VCOMP = Upper clamp Gain (2) VMULT = 1 V, VCOMP = 4 V 0.375 0.45 0.525 1/V TJ = 25 °C 2.475 2.5 2.525 2.455 2.545 2.2 2.34 V/V Error amplifier VINV IINV Voltage feedback input threshold 10.3 V < Vcc < 22.5 V Line regulation Vcc = 10.3 V to 22.
L6563H Electrical characteristics Electrical characteristics (continued) Table 4. Symbol Parameter Test condition Min. Typ. Max. Unit VPFC_OK_E Enable threshold (1) voltage rising 0.15 0.38 V VPFC_OK_E Enable threshold (1) voltage rising Tj = 25 °C 0.21 0.27 0.32 V VPFC_OK = VPFC_OK_S 1.61 1.66 1.71 mV VFFD Feedback failure detection threshold (VINV falling) Zero current detector VZCDH Upper clamp voltage IZCD = 2.5 mA 5.0 5.7 VZCDL Lower clamp voltage IZCD = - 2.5 mA -0.
Electrical characteristics Table 4. L6563H Electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit Voltage feedforward VVFF Linear operation range ΔV Dropout VMULTpk-VVFF 0.8 3 Vcc < VccOn 800 Vcc > or = to VccOn 20 V mV ΔVVFF Line drop detection threshold Below peak value 40 70 100 mV ΔVVFF Line drop detection threshold Below peak value TJ = 25 °C 50 70 90 mV 10 12.5 Internal discharge resistor TJ = 25 °C 7.
L6563H Typical electrical performance 5 Typical electrical performance Figure 4. IC consumption vs VCC Figure 5. 100 IC consumption vs TJ 10 Operating 10 Quiescent Disabled or during OV P 1 Co=1nF f =70kHz Tj = 25°C I cc [m A] VCC=12V Co = 1nF f =70kHz I c current (m A) 1 0.1 Latched off 0.1 Before Start up 0.01 VccOFF VccON 0.01 0. 001 0 5 10 15 20 25 -50 30 -25 0 25 50 Figure 6. 75 100 125 150 175 Tj (C) Vcc [V ] Vcc Zener voltage vs TJ Figure 7.
Typical electrical performance Figure 8. L6563H Feedback reference vs TJ Figure 9. 2. 6 E/A output clamp levels vs TJ 7 Uper Clam p 6 VCC = 12V 2.55 5 V COM P (V ) pi n INV (V ) V CC = 12V 2. 5 4 3 Lower Clamp 2 2.45 1 0 2. 4 -50 -25 0 25 50 75 Tj (C) 100 125 150 -50 175 -25 0 25 50 75 100 Figure 10. UVLO saturation vs TJ 150 175 Figure 11. OVP levels vs TJ 2. 5 1 0.9 2. 48 VCC = 0V 0.8 OV P T h 2. 46 P FC_OK l evels (V ) 0.7 0.6 V 125 Tj (C) 0.5 0.4 2. 44 2.
L6563H Typical electrical performance Figure 12. Inductor saturation threshold vs TJ Figure 13. Vcs clamp vs TJ 1.9 1. 4 1.8 1.7 1. 3 VCSx (V ) CS pi n (V ) 1.6 1.5 VCC = 12V VCOMP =Upper clamp 1. 2 1.4 1.3 1. 1 1.2 1.1 1 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 Figure 14. ZCD sink/source capability vs TJ 100 125 150 175 Figure 15.
Typical electrical performance L6563H Figure 16. TBO clamp vs TJ Figure 17. VVFF - VTBO dropout vs TJ 5 3.5 4 3 3.25 2 mV 1 V 3 0 -1 -2 2.75 -3 -4 -5 2.5 -50 -25 0 25 50 Tj (C) 75 100 125 150 -50 175 Figure 18. IINV - ITBO current mismatch vs TJ -25 0 25 50 75 100 125 150 175 T j (C) Figure 19. IINV - ITBO mismatch vs ITBO current 0 -1.6 VCC = 12V -1.8 -1 100*{I(I NV )-I(TBO)}/I (TBO) [ % ] 100*{I(INV)-I(TBO)}/I(TBO) [ % ] -0.5 I TBO = 200uA -1.
L6563H Typical electrical performance Figure 20. R discharge vs TJ Figure 21. Line drop detection threshold vs TJ 20 90 18 80 16 70 14 60 50 mV kOhm 12 10 40 8 30 6 20 4 10 2 0 0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 Figure 22. VMULTpk - VVFF dropout vs TJ 100 125 150 175 150 175 Figure 23. PFC_OK threshold vs TJ 2 0.4 1. 5 0.35 1 0.3 0. 5 0.25 Th (V ) ⎯ (m V) 75 Tj (C) Tj (C) 0 ON 0.2 -0. 5 0.15 -1 0.1 -1. 5 0.
Typical electrical performance L6563H Figure 24. PFC_OK FFD threshold vs TJ Figure 25. PWM_LATCH high saturation vs TJ 2 10 1.9 9 1.8 8 1.7 7 V VFFD Th (V ) VCC = 12V 1.6 6 1.5 5 1.4 -50 -25 0 25 50 75 100 12 5 150 Isource =250uA 4 1 75 -50 Tj (C) Figure 26. RUN threshold vs TJ Isource =500uA -25 0 25 50 75 T j (C) 100 125 150 175 Figure 27. PWM_STOP low saturation vs TJ 0. 25 1 ON 0.2 VCC = 12V Isink = 0. 5m A 0.8 OFF V V 0. 15 VCC = 12V 0.1 0.6 0.
L6563H Typical electrical performance Figure 28. Multiplier characteristics @ VFF = 1 V Figure 29. Multiplier characteristics @ VFF = 3 V 700 1. 2 VCOMP 1. 1 V COM P Upper voltage cl amp 1 600 Upper vo ltage 5 .5 5 .0V 0. 9 4.5 V 500 4. 0V 400 0. 8 V CS (V ) V CS (m V) 5. 5V 0. 7 0. 6 0. 5 5. 0V 4. 5V 300 3.5 V 4. 0V 0. 4 200 0. 3 3. 5V 0. 2 3.0 100 3. 0V 0. 1 2. 6V 2.6 V 0 0 0 0. 1 0.2 0. 3 0. 4 0.5 0.6 0.7 0. 8 0.9 1 1.1 0 0. 5 1 1.
Typical electrical performance L6563H Figure 32. Gate drive output saturation vs TJ Figure 33. Delay to output vs TJ 12 300 High level 10 250 TD(H-L) (n s) V 8 6 200 VCC = 12V 150 4 100 Low level 2 50 0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 Figure 34. Start-up timer period vs TJ 50 75 100 125 150 175 Tj (C) Tj (C) Figure 35.
L6563H Typical electrical performance Figure 36. VCC restart voltage vs TJ Figure 37.
Application information L6563H 6 Application information 6.1 Overvoltage protection Normally, the voltage control loop keeps the output voltage Vo of the PFC pre-regulator close to its nominal value, set by the ratio of the resistors R1 and R2 of the output divider. A pin of the device (PFC_OK) has been dedicated to monitor the output voltage with a separate resistor divider (R3 high, R4 low, see Figure 38). This divider is selected so that the voltage at the pin reaches 2.
L6563H 6.2 Application information Feedback failure protection (FFP) The OVP function above described handles “normal” over voltage conditions, i.e. those resulting from an abrupt load/line change or occurring at start-up. In case the overvoltage is generated by a feedback disconnection, for instance when the upper resistor of the output divider (R1) fails open, comparator detects the voltage at pin INV. If the voltage is lower than 1.
Application information L6563H Figure 39.
L6563H Application information The twice-mains-frequency (2•fL) ripple appearing across CFF is triangular with a peak-topeak amplitude that, with good approximation, is given by: ΔVFF = 2 VMULTpk 1 + 4fLRFF CFF where fL is the line frequency.
Application information 6.4 L6563H THD optimizer circuit The L6563H is provided with a special circuit that reduces the conduction dead-angle occurring to the AC input current near the zero-crossings of the line voltage (crossover distortion). In this way the THD (total harmonic distortion) of the current is considerably reduced. A major cause of this distortion is the inability of the system to transfer energy effectively when the instantaneous line voltage is very low.
L6563H Application information Figure 42. THD optimization: standard TM PFC controller (left side) and L6563H (right side) Input current Input current Rectified mains voltage Rectified mains voltage Imains Input current Imains Input current Vdrain MOSFET's drain voltage Vdrain MOSFET's drain voltage Essentially, the circuit artificially increases the ON-time of the power switch with a positive offset added to the output of the multiplier in the proximity of the line voltage zero-crossings.
Application information L6563H V(TBO)/RT, that is internally 1:1 mirrored and sunk from pin INV (#1) input of the L6563H's error amplifier. In this way, when the mains voltage increases the voltage at TBO pin increases as well and so does the current flowing through the resistor connected between TBO and GND. Then a larger current is sunk by INV pin and the output voltage of the PFC pre-regulator is forced to get higher.
L6563H Application information Figure 43. Tracking boost block 42!#+).' "//34 #522%.4 -)22/2 4"/ )4"/ #/-0 "5&&%2 )4"/ FROM 6&& 6 TO -ULTIPLIER 24 ).6 6 %RROR !MPLIFIER 6/54 2 2 !- V Figure 44. Tracking output voltage vs Input voltage characteristic with TBO 9R 9R [ 9R 9LQ 9R 9LQ 9LQ 9LQ 9LQ [ !- V 6.
Application information L6563H occasionally slightly saturate when the PFC stage is restarted because of a larger load demand. This happens when the restart occurs at an unfavorable line voltage phase, i.e. when the output voltage is significantly below the rectified peak voltage. As a result, in the boost inductor the inrush current coming from the bridge rectifier adds up to the switched current and, furthermore, there is little or no voltage available for demagnetization.
L6563H Application information Figure 46. Interface circuits that let dc-dc converter's controller IC drive L6563H in burst mode 3)&B2. / $ / + 3)&B6723 581 3)&B2. / / + 3)&B6723 581 !- V The third communication line is the pin PWM_STOP (#11), which works in conjunction with the pin RUN (#12). The purpose of the PWM_STOP pin is to inhibit the PWM activity of both the PFC stage and the cascaded dc-dc converter.
Application information L6563H Figure 48.
L6563H Application information In table 1 it is possible to find a summary of all of the above mentioned working conditions that cause the device to stop operating. Figure 50. Brownout protection (master PFC) L6563H 12 RUN RUN 12 L6563H 6.8 High-voltage start-up generator Figure 51 shows the internal schematic of the high-voltage start-up generator (HV generator).
Application information L6563H Figure 52. Timing diagram: normal power-up and power-down sequences 9+9 5HFWLILHG LQSXW YROWDJH ,QSXW VRXUFH LV UHPRYHG KHUH %XON FDS YROWDJH 9+9VWDUW 9FF SLQ 'F GF ORVHV UHJXODWLRQ KHUH W 9FF21 9FF2)) 9FFUHVWDUW W *' SLQ +9 FRQQHFWHG WR EXON FDS +9B(1 W +9 FRQQHFWHG WR UHFWLILHG LQSXW YROWDJH W 9FFB2. ,FKDUJH W P$ 1RUPDO RSHUDWLRQ 3RZHU RQ 3RZHU RII W !- V As the Vcc voltage reaches the start-up threshold (12 V typ.
L6563H Application information consumption and drops more until the Vccrestart threshold is tripped. Now, the high voltage start-up generator restarts and when the Vcc crosses again its turn on threshold the IC starts switching. In this manner the power is transferred from mains to PFC output only during a short time for each Trep cycle. Figure 53.
Application information Table 5. L6563H Summary of L6563H idle states Typical IC PWM_LATCH PWM_STOP Condition Caused or revealed bey IC behavior Restart condition consumption Status Status UVLO Vcc < VccOff Disabled Vcc > VccOn 90 µA Off High Feedback disconnected PFC_OK > VPFC_OK_S AND INV < 1.66V Latched Vcc < Vccrestart then Vcc > VccOn 180 µA High High Standby PFC_OK < VPFC_OK_D PFC_OK > VPFC_OK_E 1.5 mA Off High AC brownout RUN < VDIS RUN > VEN 1.
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Application examples and ideas L6563H Figure 56. L6563H 100 W TM PFC evaluation board: compliance to EN61000-3-2 standard Me as ur e d v alue Figure 57. L6563H 100 W TM PFC evaluation board: compliance to JEITA-MITI standard EN61 000 -3- 2 clas s -D lim it s Measured value JEITA-MITI Class-D limits 10 Harmonic Current [A] Harmonic Current [A] 1 0 .1 0.01 0.001 1 0.1 0.01 0.001 0.0001 0 .
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L6563H Application examples and ideas Figure 62.
Application examples and ideas L6563H R D 7BD C on fid 44/49 T AF en tia l Figure 63.
L6563H 8 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Table 6. SO16 mechanical data mm Dim. Min. Typ. A Max. 1.75 A1 0.1 A2 1.25 b 0.31 0.51 c 0.17 0.25 D 9.8 9.9 10 E 5.8 6 6.2 E1 3.8 3.
Package mechanical data L6563H Figure 64.
L6563H 9 Ordering codes Ordering codes Table 7.
Revision history 10 L6563H Revision history Table 8. 48/49 Document revision history Date Revision Changes 22-Jul-2009 1 Initial release. 01-Feb-2010 2 Updated Table 4 on page 11 21-Dec-2010 3 Updated Figure 1 on page 1, Figure 24 on page 20, Table 3 on page 8, Table 4 on page 11, Table 5 on page 34 and Section 6.
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