AN3063 Application note 100 W transition-mode PFC pre-regulator with the L6563H Introduction This application note describes a demonstration board based on the transition-mode PFC controller L6563H and presents the results of its bench demonstration. The board implements a 100 W, wide-range mains input, PFC pre-conditioner suitable for ballast, adapters, flatscreen displays, and all SMPS having to meet the IEC61000-3-2 or the JEITAMITI regulation.
Contents AN3063 Contents 1 Main characteristics and circuit description . . . . . . . . . . . . . . . . . . . . . 4 2 Electrical diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 Test results and significant waveforms . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 Harmonic content measurement . . . . . . . . . . . . . . . . . . . .
AN3063 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41.
Main characteristics and circuit description 1 AN3063 Main characteristics and circuit description The main characteristics of the SMPS are listed below: ● Line voltage range: 90 to 265 Vac ● Minimum line frequency (fL): 47 Hz ● Regulated output voltage: 400 V ● Rated output power: 100 W ● Maximum 2fL output voltage ripple: 20 V pk-pk ● Hold-up time: 10 ms (VDROP after hold-up time: 300 V) ● Minimum switching frequency: 40 kHz ● Minimum estimated efficiency: 92% (at Vin = 90 Vac, Pout = 10
AN3063 Main characteristics and circuit description C13, R27 and R32, connected to pin #5 VFF, complete an internal peak-holding circuit that derives the information on the RMS mains voltage. The voltage signal at this pin, a DC level equal to the peak voltage on pin #3 (MULT), is fed to a second input to the multiplier for the 1/V2 function necessary to compensate the control loop gain dependence on the mains voltage.
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Bill of material Table 1. EVL6563H-100W TM PFC demonstration board bill of material Doc ID 16261 Rev 3 Part type/part value Case/package Description Supplier C1 470N DWG X2 - FLM CAP - R46-I 3470--M1- ARCOTRONICS C4 470N DWG X2 - FLM CAP - R46-I 3470--M1- ARCOTRONICS C2 2N2 DWG Y1 - SAFETY CAP. DE1E3KX222M muRata C3 2N2 DWG Y1 - SAFETY CAP. DE1E3KX222M muRata C5 470N - 400 V DWG 400 V - FLM CAP - B32653A4474 EPCOS C6 47 µF - 450 V Dia. 18 x 31.
EVL6563H-100W TM PFC demonstration board bill of material (continued) Doc ID 16261 Rev 3 Part type/part value Case/package Description Supplier F1 FUSE 4A DWG Fuse T4A - time delay Wichmann HS1 HEAT-SINK DWG Heatsink for D1 and Q1 JP1 N.M. Not mounted JP2 Wire jumper Wire jumper - insulated J1 MKDS 1,5/ 3-5,08 DWG PCB term. block, screw conn., pitch 5 mm - 3 W PHOENIX CONTACT J2 MKDS 1,5/ 2-5,08 DWG PCB term. block, screw conn.
EVL6563H-100W TM PFC demonstration board bill of material (continued) Doc ID 16261 Rev 3 Des. Part type/part value Case/package Description Supplier R14 27 kΩ 0805 SMD STD film res - 1/8 W - 1% - 100 ppm/°C VISHAY R15 51 kΩ 1206 SMD STD film res - 1/4 W - 1% - 100 ppm/°C VISHAY R18 82 kΩ 0805 SMD STD film res - 1/8 W - 5% - 250 ppm/°C VISHAY R19 51 kΩ 1206 SMD STD film res - 1/4 W - 5% - 250 ppm/°C VISHAY R20 N.M.
Test results and significant waveforms AN3063 4 Test results and significant waveforms 4.1 Harmonic content measurement One of the main purposes of a PFC pre-conditioner is the correction of input current distortion, decreasing the harmonic contents below the limits of the relevant regulations. Therefore, this demonstration board has been tested according to the European standard EN61000-3-2 class-D and Japanese standard JEITA-MITI Class-D, at full load at both the nominal input voltage mains.
AN3063 Test results and significant waveforms For user reference, waveforms of the input current and voltage at the nominal input voltage mains and nominal load conditions are shown in Figure 5 and 6. Figure 5. EVL6563H-100W TM PFC: input current waveform at 230 V, 50 Hz, 100 W load Figure 6.
Test results and significant waveforms AN3063 The measured efficiency shown in Figure 9, measured according to the ES-2 requirements, is very good at all load and line conditions. At full load it is always higher than 93% making this design suitable for high-efficiency power supplies. The average efficiency, calculated according to the ES-2 requirements, at different nominal mains voltages is shown in Figure 10. Figure 9. EVL6563H-100W TM PFC: efficiency Figure 10. EVL6563H-100W TM PFC: average vs.
AN3063 Test results and significant waveforms power factor. On both the drain voltage traces, close to the zero-crossing points of the sine wave, it is possible to note the action of the THD optimizer embedded in the L6563H. It is a circuit that minimizes the conduction dead-angle of the AC input current near the zerocrossings of the line voltage (crossover distortion). In this way, the THD (total harmonic distortion) of the current is considerably reduced.
Test results and significant waveforms AN3063 Figure 14. EVL6563H-100W TM PFC: Vds and inductor current at 230 Vac, 50 Hz, full load Figure 15. EVL6563H-100W TM PFC: Vds and inductor current at 230 Vac, 50 Hz, full load (detail) CH4: Q1 drain voltage CH4: Q1 drain voltage CH2: MULT voltage - pin #3 CH2: MULT voltage - pin #3 CH1: L2 inductor current CH1: L2 inductor current In Figure 16 and 17 the detail of the waveforms at switching frequency shows the operation of transition-mode control.
AN3063 Test results and significant waveforms Figure 16. EVL6563H-100W TM PFC: Vds and inductor current at 100 Vac, 50 Hz, full load Figure 17. EVL6563H-100W TM PFC: Vds and inductor current at 230 Vac, 50 Hz, full load CH1: GD - pin #15 CH1: GD - pin #15 CH2: ZCD - pin #13 CH2: ZCD - pin #13 CH3: CS - pin #4 CH3: CS - pin #4 CH4: L2 inductor current CH4: L2 inductor current 4.
Test results and significant waveforms AN3063 ripple at twice the mains frequency that will cause distortion of the current reference (resulting in high THD and poor PF). If it is too large, there will be a considerable delay in setting the right amount of feed-forward, resulting in excessive overshoot and undershoot of the pre-regulator's output voltage in response to large line voltage changes. Clearly a tradeoff was required.
AN3063 Test results and significant waveforms Figure 21 shows the circuit behavior in case of a mains dip. As previously described, the internal circuitry has detected the decreasing of the mains voltage and it has activated the CFF internal fast discharge. As visible, in that case the output voltage changes but in few mains cycles it comes back to the nominal value. The situation is different if we check the performance of a controller without the VFF function.
Test results and significant waveforms AN3063 Comparing Figure 22 and 23 we can see that the input current of the latter has a better shape and the 3rd harmonic current distortion is not noticeable. This demonstrates the benefits of the new voltage feed-forward circuit integrated in the L6563H. Allowing a fast response to mains disturbances but using a quite long VFF time constant provides also very low THD and high PF at same time as confirmed by the measurements below. Figure 22.
AN3063 Test results and significant waveforms Figure 24. EVL6563H-100W startup attempt at 80 Vac, 60 Hz, full load CH1: PFC output voltage CH2: Vcc voltage (pin #16) CH3: RUN (pin #12) CH4: gate drive (pin #15) In Figure 24 a startup tentative below the threshold is captured. As visible, at startup the RUN pin does not allow PFC startup. In Figure 25 and 26 the waveforms of the circuit during operation of the brownout protection are captured.
Test results and significant waveforms 4.4 AN3063 Startup operation On the L6563H, the high-voltage startup function is implemented. The HVS (pin #9), is directly connected to the DC bulk voltage and at startup, an internal high-voltage current source charges C10 and C11 until the L6563H turn-on voltage threshold is reached, at which point the high-voltage current source is automatically switched off.
AN3063 Test results and significant waveforms voltage exceeds a preset value (VOVP), usually larger than the maximum Vout that can be expected, also including worst-case load/line transients. ● For the EVL6563H-100W we have: – VO = 400 V – VOVP = 434 V – Select: R3+R4+R11 = 8.8 MΩ then: – R15 = 8.8 MΩ ·2.5/(434-2.5) = 51 kΩ Once this function is triggered, the gate drive activity is immediately stopped until the voltage on the pin PFC_OK drops below 2.4 V. An example is given in Figure 29.
Test results and significant waveforms AN3063 Figure 29. EVL6563H-100W load transient at 115 Vac, 60 Hz, full load to no load CH1: PFC output voltage CH2: PFC_OK (pin #7) CH3: gate drive (pin #15) CH4: Iout The event of an open loop is captured in Figure 30 and 31. We can notice the protection intervention, latching the operation of the L6563H. As highlighted in Figure 31 the L6563H is supplied by the HVS circuit, maintaining Vcc value above its UVLO threshold.
AN3063 4.6 Test results and significant waveforms TBO (tracking boost option) To use the TBO function on L6563H, a dedicated input of the multiplier is available on pin #6 (TBO). The function can be implemented by simply connecting a resistor (RT) between the TBO pin and ground.
Test results and significant waveforms AN3063 Figure 32. EVL6563H on/off control by a cascaded converter controller via the PFC_OK or RUN pin 25. , ( 0&#?/+ 0&#?/+ 0&#?34/0 0&#?34/0 , ! , 25. , ( !- V The third communication line is the PWM_STOP (pin #11), which works in conjunction with the RUN (pin #12).
AN3063 5 Layout hints Layout hints The layout of any converter is a very important phase in the design process needing attention by the design engineers like any other design phase. Even if it the layout phase sometimes looks time-consuming, a good layout does indeed save time during the functional debugging and the qualification phases. Additionally, a power supply circuit with a correct layout needs smaller EMI filters or less filter stages which allows consistent cost saving.
Layout hints AN3063 Figure 35.
AN3063 6 EMI filtering and conducted EMI pre-compliance measurements EMI filtering and conducted EMI pre-compliance measurements The following figures show the peak measurement of the conducted noise at full load and nominal mains voltages for both mains lines. The limits shown in the diagrams are EN55022 class-B which is the most popular regulation for domestic equipment using a two-wire mains connection.
EMI filtering and conducted EMI pre-compliance measurements AN3063 Figure 39. EVL6563H-100W CE peak Figure 38. EVL6563H-100W CE peak measurement at 230 Vac, 50 Hz, full measurement at 230 Vac, 50 Hz, full load, neutral load, phase !- V !- V As visible in the diagrams, in all test conditions there is a good margin of the measures with respect to the limits. The measurements have been done in peak detection to speed up the sweep, otherwise taking a long time.
AN3063 PFC coil specifications 7 PFC coil specifications 7.1 General description and characteristics 7.2 ● Applications: consumer, home appliance ● Transformer type: open ● Coil former: vertical type, 6+6 pins ● Max. temp. rise: 45 °C ● Max. operating ambient temp.: 60 °C ● Mains insulation: N.A. ● Unit finish: varnish Electrical characteristics ● Converter topology: boost, transition mode ● Core type: PQ26/20 - PC44 ● Min.
PFC coil specifications 7.4 AN3063 Winding characteristics Table 2. Winding characteristics Pins Winding RMS current Number of turns Wire type 5-9 Primary(1) 1.4 ARMS 57.5 - fit Multi stranded #7 x φ 0.20 mm 11 - 3 Aux (2) 0.05 ARMS 5.5 - spaced φ 0.28 mm 1. Primary winding external insulation: 2 layers of polyester tape 2. Aux winding is wound on top of primary winding. External insulation with 2 layers of polyester tape 7.
AN3063 8 References References 1. L6563H datasheet. 2. AN3027 “How to design a Transition Mode PFC pre-regulator with the L6563S and L6563H”.
Revision history 9 AN3063 Revision history Table 3. 32/33 Document revision history Date Revision Changes 28-May-2010 1 Initial release. 03-Jun-2010 2 Modified titles for: Figure 12, 13, 14 and 15. 06-Sep-2010 3 Content reworked to improve readability.
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