Datasheet

AN3329 Functional check
Doc ID 18376 Rev 1 19/47
L6564 signals are shown in Figure 33 and 34 for reference.
Figure 35 shows voltages on the VFF (#5), CS (#4), COMP (#2), and MULT (#3) pins along
a line half-period at 115 Vac and 230 Vac respectively. Voltage feed-forward compensates
for the gain and crossover frequency variation with the line voltage, since the power stage
gain of PFC pre-regulators varies with the square of the RMS input voltage. Therefore, a DC
voltage equal to the peak of the MULT (#3) pin is derived on the VFF (#5) pin and fed into a
square/divider circuit making the COMP signal almost line-independent and improving the
dynamic behavior. That is emphasized in Figure 36, which illustrates voltage on the MULT
(#3) pin at the peak of the line voltage matching that on the VFF pin.
Figure 31. PFC Vds and inductor current at
230 Vac - 50 Hz, full load
Figure 32. PFC Vds and inductor current at
230 Vac - 50 Hz, full load - detail
CH2: MULT (pin #3)
CH3: CS (pin #4)
CH4: L1 inductor current
CH1: Q1 drain voltage
CH3: CS (pin #4)
CH1: Q1 drain voltage
CH2: MULT (pin #3)
CH4: L1 inductor current
Figure 33. L6564 signals-1 at 115 Vac - 60 Hz,
full load
Figure 34. L6564 signals-2 at 115 Vac - 60 Hz,
full load
CH2: ZCD (pin #7)
CH3: MULT (pin #3)
CH4: CS (pin #4)
CH1: GD (pin #9)
CH3: MULT (pin #3)
CH1: GD (pin #9)
CH2: ZCD (pin #7)
CH4: CS (pin #4)