Datasheet

Functional check AN3329
18/47 Doc ID 18376 Rev 1
Power factor corrector stage
Figure 29 shows the PFC MOSFET's drain voltage, inductor current, and voltages on the
CS (#4) and MULT (#3) pins along a line half-period at 115Vac. Low current distortion and
high power factor are achieved as the peak inductor current waveform follows the MULT pin.
THD (total harmonic distortion) is considerably reduced by the L6564 THD optimizer.
In Figure 30 the same signals are captured at the top of the input sine wave. Transition
mode control makes the inductor work on the boundary between continuous and
discontinuous conduction mode. When the PFC MOSFET turns on, the inductor current
ramps up, until the voltage on the current sense input reaches the reference level
programmed by the internal multiplier block. At that point, the PWM comparator changes
state, turning off the power switch. During the MOSFET off-time, the current ramps down
until it reaches zero, so the inductor is demagnetized. The zero current detection (ZCD)
circuit detects that point by monitoring the voltage across the inductor auxiliary winding,
which falls to zero when the current reaches zero, due to the resonance between the
inductor and the drain capacitance. Once the demagnetization point is detected by the
L6564 internal logic, the signal on ZCD drives the MOSFET on again and another switching
cycle begins. A significant advantage of TM operation is the possibility to work in ZVS: if the
instantaneous input voltage of the converter is lower than the inductor voltage, the ZVS
(zero voltage switching) condition is achieved, decreasing MOSFET commutation losses.
However, if the instantaneous input voltage is higher than the inductor voltage the MOSFET
is turned on at the minimum voltage, on the valley point of the resonance, still minimizing the
transition losses, as seen in Figure 32.
Figure 31 and Figure 32 show the same waveforms at 230 Vac. As the input voltage is
higher than the inductor voltage, it is possible to observe the boost inductor resonating with
the total drain capacitance with an amplitude of twice the inductor voltage on the offset of
the input voltage. In order to maximize efficiency the RC network connected to the ZCD (#7)
pin is tuned to make the turn-on of the MOSFET occur just on the valley of the drain voltage.
Figure 29. PFC Vds and inductor current at
115 Vac - 60 Hz, full load
Figure 30. PFC Vds and inductor current at
115 Vac - 60 Hz, full load - detail
CH2: MULT (pin #3)
CH3: CS (pin #4)
CH4: L1 inductor current
CH1: Q1 drain voltage
CH3: CS (pin #4)
CH1: Q1 drain voltage
CH2: MULT (pin #3)
CH4: L1 inductor current