Datasheet

L6474 Functional description
Doc ID 022529 Rev 3 25/52
6.13 Programmable DMOS slew-rate, dead-time and blanking-time
Using the POW_SR parameter in the CONFIG register, it is possible to set the commutation
speed of the power bridges output (see Ta bl e 25).
6.14 Integrated analog to digital converter
The L6474 integrates a NADC bit ramp-compare analog to digital converter with a reference
voltage equal to VREG. The analog to digital converter input is available through the ADCIN
pin and the conversion result is available in the ADC_OUT register (see Section 9.1.13).
Sampling frequency is equal to the clock frequency divided by 512.
The ADC_OUT value can be used for the torque regulation or is at the user’s disposal.
6.15 Internal voltage regulator
The L6474 integrates a voltage regulator which generates a 3 V voltage starting from the
motor power supply (VSA and VSB). In order to make the voltage regulator stable, at least
22 µF should be connected between the VREG pin and ground (suggested value is 47 µF).
The internal voltage regulator can be used to supply the VDD pin in order to make the
device digital output range 3.3 V compatible (Figure 8). A digital output range 5 V
compatible can be obtained connecting the VDD pin to an external 5 V voltage source. In
both cases, a 10 µF capacitance should be connected to the VDD pin in order to obtain a
correct operation.
The internal voltage regulator is able to supply a current up to I
REG,MAX, internal logic
consumption included (I
logic
). When the device is in standby mode the maximum current that
can be supplied is I
REG
,
STBY
, internal consumption included (I
logic
,
STBY
).
If an external 3.3 V regulated voltage is available, it can be applied to the VREG pin in order
to supply all the internal logic and avoid power dissipation of the internal 3 V voltage
regulator (Figure 8). The external voltage regulator should never sink current from the
VREG pin.
Figure 8. Internal 3 V linear regulator
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