Datasheet

Pin connection L6472
18/70 DocID022729 Rev 3
3 STBY\RST Logic input
Standby and reset pin. LOW logic level resets the logic and puts
the device into standby mode. If not used, it should be connected
to VDD
25 STCK Logic input Step-clock input
EPAD Exposed pad Ground Internally connected to PGND, AGND and DGND pins
Table 6. Pin description (continued)
No. Name Type Function