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This is information on a product in full production.

December 2013 DocID022729 Rev 3 1/70

L6472

dSPIN™ fully integrated microstepping motor driver

Datasheet - production data

Features

 Operating voltage: 8 - 45 V

 7.0 A output peak current (3.0 A

r.m.s.

)

 Low R

DS(on)

Power MOSFETs

 Programmable speed profile

 Programmable Power MOSFET slew rate

 Up to 1/16 microstepping

 Predictive current control with adaptive decay

 Non dissipative current sensing

 SPI interface

 Low quiescent and standby currents

 Programmable non dissipative overcurrent

protection on all Power MOSFETs

 Two levels of overtemperature protection

Applications

 Bipolar stepper motor

Description

The L6472 device, realized in analog mixed

signal technology, is an advanced fully integrated

solution suitable for driving two-phase bipolar

stepper motors with microstepping. It integrates

a dual low R

DS(on)

DMOS full bridge with all of the

power switches equipped with an accurate

on-chip current sensing circuitry suitable for non

dissipative current control and overcurrent

protection. Thanks to a new current control,

a 1/16 microstepping is achieved through an

adaptive decay mode which outperforms

traditional implementations. The digital control

core can generate user defined motion profiles

with acceleration, deceleration, speed or target

position, easily programmed through a dedicated

All application commands and data registers,

including those used to set analog values

(i.e. current control value, current protection trip

point, deadtime, etc.) are sent through a standard

5-Mbit/s SPI.

A very rich set of protections (thermal, low bus

voltage, overcurrent) makes the L6472 device

“bullet proof”, as required by the most demanding

motor control applications.

HTSSOP28

POWERSO36

Table 1. Device summary

Order codes Package Packing

L6472H HTSSOP28 Tube

L6472HTR HTSSOP28 Tape and reel

L6472PD POWERSO36 Tube

L6472PDTR POWERSO36 Tape and reel

www.st.com

Summary of content (70 pages)

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L6472 dSPIN™ fully integrated microstepping motor driver Datasheet - production data Applications  Bipolar stepper motor Description HTSSOP28 POWERSO36 Features  Operating voltage: 8 - 45 V  7.0 A output peak current (3.0 A r.m.s.
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Contents L6472 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Thermal data . . . . . . . . . . . . . . . . . . .
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L6472 Contents 6.9 Overcurrent detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.10 Undervoltage lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.11 Thermal warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.12 Reset and standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.13 External switch (SW pin) . . . . . . . . . . . . . . . . . . . .
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Contents L6472 9.2 9.1.14 ADC_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.1.15 OCD_TH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.1.16 STEP_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.1.17 ALARM_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.1.18 CONFIG . . . . . . . . . . .
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L6472 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47.
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List of tables Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. 6/70 L6472 ResetDevice command structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 SoftStop command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 HardStop command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 SoftHiZ command structure .
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L6472 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 HTSSOP28 pin connection (top view) . . . . . . . . . . . .
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Block diagram 1 L6472 Block diagram Figure 1. Block diagram 9'' 26&,1 0+] 2VFLOODWRU 26&287 $'&,1 95(* 9%227 &KDUJH SXPS ([W 2VF GULYHU &ORFN JHQ $'& 67%< 567 &3 96$ 9 9ROWDJH 5HJ )/$* 9 ERRW 9 ERRW +6 $ 96$ +6 $ 5HJLVWHUV 287 $ 9 '' +6 $ 287 $ /6 $ +6 $ /6 $ /6 $ /6 $ &RQWURO /RJLF 3*1' 96% +6 % /6 % &6 9 ERRW 9 ERRW 96% +6 % /6 % 63, &. 6'2 +6 % +6 % 287 % 6', 287 % %86< 6<1& 67&.
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L6472 Electrical data 2 Electrical data 2.1 Absolute maximum ratings Table 2. Absolute maximum ratings Symbol VDD VS VGND, diff Parameter Test condition Value Unit 5.5 V 48 V ±0.3 V Logic interface supply voltage Motor supply voltage VSA = VSB = VS Differential voltage between AGND, PGND and DGND Vboot Bootstrap peak voltage 55 V VREG Internal voltage regulator output pin and logic supply voltage 3.6 V Integrated ADC input voltage range (ADCIN pin) -0.3 to +3.
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Electrical data 2.3 L6472 Thermal data Table 4. Thermal data Symbol RthJA Parameter Thermal resistance junction-ambient Package Typ. HTSSOP28(1) 22 POWERSO36(2) 12 Unit °C/W 1. HTSSOP28 mounted on the EVAL6472H Rev 1.0 board: four-layer FR4 PCB with a dissipating copper surface of about 40 cm2 on each layer and 15 via holes below the IC. 2. POWERSO36 mounted on the EVAL6472PD Rev 1.
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L6472 3 Electrical characteristics Electrical characteristics VSA = VSB = 36 V; VDD = 3.3 V; internal 3 V regulator; TJ = 25 °C, unless otherwise specified. Table 5. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit General VSthOn VS UVLO turn-on threshold 7.5 8.2 8.9 V VSthOff VS UVLO turn-off threshold 6.6 7.2 7.8 V VSthHyst VS UVLO threshold hysteresis 0.7 1 1.3 V Iq Quiescent motor supply current 0.5 0.
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Electrical characteristics L6472 Table 5. Electrical characteristics (continued) Symbol tf SRout_r SRout_f Parameter Fall time Test condition (3) Output rising slew rate Output falling slew rate Min. Typ.
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L6472 Electrical characteristics Table 5. Electrical characteristics (continued) Symbol IIL Parameter Low logic level input current Test condition (5) VOL Low logic level output voltage (6) VOH High logic level output voltage RPU RPD Ilogic Ilogic,STBY fSTCK VIN = 0 V Min. Typ. Max. Unit -1 µA VDD = 3.3 V, IOL = 4 mA 0.3 VDD = 5 V, IOL = 4 mA 0.3 VDD = 3.3 V, IOH = 4 mA 2.4 VDD = 5 V, IOH = 4 mA 4.
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Electrical characteristics L6472 Table 5. Electrical characteristics (continued) Symbol Parameter tdisSDO Data output disable time tvSDO Data output valid time(7) tholSDO Data output hold time Test condition Min. Typ. (7) (7) Max. Unit 47 ns 57 ns 37 ns Switch input (SW) RPUSW SW input pull-up resistance SW = GND 60 85 110 k Current control ISTEP,max Max. programmable reference current 4 A ISTEP,min Min. programmable reference current 31 mA 6 A 0.37 5 A 0.
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L6472 Electrical characteristics Table 5. Electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit Integrated analog-to-digital converter NADC Analog-to-digital converter resolution 5 bit VADC,ref Analog-to-digital converter reference voltage VREG V fS Analog-to-digital converter sampling frequency fOSC/ 512 kHz 1. Accuracy depends on oscillator frequency accuracy. 2. Tested at 25 °C in a restricted range and guaranteed by characterization. 3.
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Pin connection 4 L6472 Pin connection Figure 2. HTSSOP28 pin connection (top view) 345 Figure 3.
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L6472 Pin connection Pin list Table 6. Pin description No. Name Type 17 VDD Power Logic output supply voltage (pull-up reference) 6 VREG Power Internal 3 V voltage regulator output and 3.3 V external logic supply 7 OSCIN Analog input Oscillator pin 1. To connect an external oscillator or clock source. If this pin is unused, it should be left floating. 8 OSCOUT Analog output Oscillator pin 2. To connect an external oscillator.
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Pin connection L6472 Table 6. Pin description (continued) No. Name Type Function 3 STBY\RST Logic input Standby and reset pin. LOW logic level resets the logic and puts the device into standby mode.
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L6472 5 Typical applications Typical applications Table 7. Typical application values Name Value CVS 220 nF CVSPOL 100 µF CREG 100 nF CREGPOL 47 µF CDD 100 nF CDDPOL 10 µF D1 Charge pump diodes CBOOT 220 nF CFLY 10 nF RPU 39 k RSW 100  CSW 10 nF Figure 4.
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Functional description L6472 6 Functional description 6.1 Device power-up At the end of power-up, the device state is the following:  Registers are set to default  Internal logic is driven by the internal oscillator and a 2 MHz clock is provided by the OSCOUT pin  Bridges are disabled (High Z)  UVLO bit in the STATUS register is forced low (fail condition)  FLAG output is forced low.
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L6472 Functional description Figure 5. Charge pump circuitry 6.4 Microstepping The driver is able to divide the single step into up to 16 microsteps. Step mode can be programmed by the STEP_SEL parameter in the STEP_MODE register (see Table 20 on page 47). Step mode can only be changed when bridges are disabled. Every time step mode is changed, the electrical position (i.e.
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Functional description L6472 Figure 6. Normal mode and microstepping (16 microsteps) Automatic full-step mode When motor speed is greater than a programmable full-step speed threshold, the L6472 switches automatically to full-step mode (see Figure 7); the driving mode returns to microstepping when motor speed decreases below the full-step speed threshold. The fullstep speed threshold is set through the FS_SPD register (see Section 9.1.9 on page 43). Figure 7.
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L6472 6.5 Functional description Absolute position counter An internal 22-bit register (ABS_POS) keeps track of the motor motion according to the selected step mode; the stored value unit is equal to the selected step mode (full, half, quarter, etc.). The position range is from -221 to +221-1 (µ) steps (see Section 9.1.1 on page 41). 6.
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Functional description 6.7 L6472 Motor control commands The L6472 can accept different types of commands:  constant speed commands (Run, GoUntil, ReleaseSW)  absolute positioning commands (GoTo, GoTo_DIR, GoHome, GoMark)  motion commands (Move)  stop commands (SoftStop, HardStop, SoftHiz, HardHiz). For detailed command descriptions refer to Section 9.2 on page 54. 6.7.
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L6472 Functional description Figure 10. Positioning command examples 6.7.3 Motion commands Motion commands produce a motion in order to perform a user-defined number of microsteps in a user-defined direction that are sent to the device together with the command (see Figure 11). The performed motor motion is compliant to programmed speed profile boundaries (acceleration, deceleration, minimum and maximum speed).
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Functional description L6472 The HardStop command stops the motor instantly, ignoring deceleration constraints and maintaining the rotor position (a holding torque is applied). The SoftHiZ command causes the motor to decelerate with a programmed deceleration value until the MIN_SPEED value is reached and then forces the bridges into highimpedance state (no holding torque is present). The HardHiZ command instantly forces the bridges into high-impedance state (no holding torque is present). 6.7.
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L6472 6.8 Functional description Internal oscillator and oscillator driver The control logic clock can be supplied by the internal 16-MHz oscillator, an external oscillator (crystal or ceramic resonator) or a direct clock signal. These working modes can be selected by the EXT_CLK and OSC_SEL parameters in the CONFIG register (see Table 25 on page 50). At power-up the device starts using the internal oscillator and provides a 2-MHz clock signal on the OSCOUT pin. Warning: 6.8.
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Functional description L6472 Figure 12. OSCIN and OSCOUT pin configurations Note: When OSCIN is UNUSED, it should be left floating. When OSCOUT is UNUSED it should be left floating. 6.9 Overcurrent detection When the current in any of the Power MOSFETs exceeds a programmed overcurrent threshold, the STATUS register OCD flag is forced low until the overcurrent event expires and a GetStatus command is sent to the IC (see Section 9.1.19 on page 52 and 9.2.20 on page 63).
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L6472 Functional description Warning: 6.10 The overcurrent shutdown is a critical protection feature. It is not recommended to disable it. Undervoltage lockout (UVLO) The L6472 provides motor supply UVLO protection. When the motor supply voltage falls below the VSthOff threshold voltage, the STATUS register UVLO flag is forced low. When a GetStatus command is sent to the IC, and the undervoltage condition expires, the UVLO flag is released (see Section 9.1.19 on page 52 and 9.2.20 on page 63).
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Functional description L6472 On exiting standby mode the bridges are disabled (HiZ flag high) and whichever motion command causes the device to exit High Z state (HardStop and SoftStop included). Warning: 6.13 It is not recommended to reset the device when outputs are active. The device should be switched to high-impedance state before being reset. External switch (SW pin) The SW input is internally pulled-up to VDD and detects if the pin is open or connected to ground (see Figure 13).
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L6472 Functional description 6.15 Integrated analog-to-digital converter The L6472 integrates an NADC bit ramp-compare analog-to-digital converter with a reference voltage equal to VREG. The analog-to-digital converter input is available through the ADCIN pin and the conversion result is available in the ADC_OUT register (see Section 9.1.13 on page 46). The sampling frequency is equal to the clock frequency divided by 512.
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Functional description 6.17 L6472 BUSY\SYNC pin This pin is an open drain output which can be used as the busy flag or synchronization signal according to the SYNC_EN bit value (STEP_MODE register). 6.17.1 BUSY operation mode The pin works as busy signal when the SYNC_EN bit is set low (default condition). In this mode the output is forced low while a constant speed, absolute positioning or motion command is under execution.
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L6472 7 Phase current control Phase current control The L6472 performs a new current control technique, named predictive current control, allowing the device to obtain the target average phase current. This method is described in detail in Section 7.1. Furthermore, the L6472 automatically selects the better decay mode in order to follow the current profile. Current control algorithm parameters can be programmed by the T_FAST, TON_MIN, TOFF_MIN and CONFIG registers (see Section 9.1.11 on page 45, 9.1.
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Phase current control L6472 At the end of the predictive ON state the power stage is set in the OFF state for a fixed time, as in a constant tOFF current control. During the OFF state both slow and fast decay can be performed; the better decay combination is automatically selected by the L6472, as described in Section 7.2.
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L6472 Phase current control Section 7.1. The maximum fast decay duration is set by the TOFF_FAST value. Figure 17. Adaptive decay - fast decay tuning W)$67 W)$67 W)$67 W)$67 $0 When two or more fast decays are performed with the present target current, the control system adds a fast decay at the end of every OFF time, keeping the OFF state duration constant (tOFF is split into tOFF,SLOW and tOFF,FAST).
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Phase current control L6472 Figure 18. Adaptive decay switch from normal to slow + fast decay mode and vice-versa 7.3 Auto-adjusted fast decay during the falling steps When the target current is decreased by a microstep change (falling step), the device performs a fast decay in order to reach the new value as fast as possible. Anyway, exceeding the fast duration may cause a strong ripple on the step change. The L6472 device automatically adjusts these fast decays reducing the current ripple.
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L6472 Phase current control Figure 19. Fast decay tuning during the falling steps 7.4 Torque regulation (output current amplitude regulation) The output current amplitude can be regulated in two ways: writing the TVAL_ACC, TVAL_DEC, TVAL_RUN and TVAL_HOLD registers or varying the ADCIN voltage value. The EN_TQREG bit (CONFIG register) sets the torque regulation method. If this bit is high, the ADC_OUT prevalue is used to regulate output current amplitude (see Section 9.1.14 on page 46).
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Serial interface 8 L6472 Serial interface The integrated 8-bit serial peripheral interface (SPI) is used for a synchronous serial communication between the host microprocessor (always master) and the L6472 (always slave). The SPI uses chip select (CS), serial clock (CK), serial data input (SDI) and serial data output (SDO) pins. When CS is high, the device is unselected and the SDO line is inactive (high-impedance). The communication starts when CS is forced low.
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L6472 Serial interface Figure 21.
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Programming manual L6472 9 Programming manual 9.1 Register and flag description Table 9 shows a map of the user registers available (detailed description in respective paragraphs from Section 9.1.1 on page 41 to Section 9.1.19 on page 52): Table 9. Register map Address [Hex] Register name Register function Len.
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L6472 Programming manual Table 9. Register map (continued) Address [Hex] Register name Register function Len. [bit] Reset [Hex] Reset value Remarks(1) R, WH R h18 CONFIG IC configuration 16 2E88 Internal oscillator, 2 MHz OSCOUT clock, supply voltage compensation disabled, overcurrent shutdown enabled, slew rate = 290 V/µs TSW = 40 µs h19 STATUS Status 16 XXXX(2) High-impedance state, UVLO/reset flag set. h1A RESERVED Reserved address h1B RESERVED Reserved address 1.
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Programming manual 9.1.3 L6472 MARK The MARK register contains an absolute position called MARK, in accordance with the selected step mode; the stored value unit is equal to the selected step mode (full, half, quarter, etc.). It is in 2's complement format and it ranges from -221 to +221-1. 9.1.4 SPEED The SPEED register contains the current motor speed, expressed in step/tick (format unsigned fixed point 0.28).
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L6472 Programming manual Equation 3 – 40 DEC  2  step  s  = ---------------------------2 tick where DEC is the integer number stored in the register and tick is 250 ns. The available range is from 14.55 to 59590 step/s2 with a resolution of 14.55 step/s2. When the device is working in infinite acceleration mode this value is ignored. Any attempt to write the register when the motor is running causes the command to be ignored and the NOTPERF_CMD flag to rise (see Section 9.1.19 on page 52). 9.1.
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Programming manual L6472 expressed in step/tick (format unsigned fixed point 0.18) and to convert it in step/s the following formula can be used. Equation 6 – 18  FSSPD + 0.5   2  step  s  = -------------------------------------------------------tick If the FS_SPD value is set to h3FF (max.) the system always works in microstepping mode (SPEED must go beyond the threshold to switch to full-step mode).
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L6472 9.1.11 Programming manual T_FAST The T_FAST register contains the maximum fast decay time (TOFF_FAST) and the maximum fall step time (FALL_STEP) used by the current control system (see Section 7.2 on page 34 and 7.3 on page 36 for details): Table 13. T_FAST register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 TOFF_FAST Bit 1 Bit 0 FAST_STEP The available range for both parameters is from 2 µs to 32 µs. Table 14.
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Programming manual 9.1.13 L6472 TOFF_MIN The TOFF_MIN register contains the minimum OFF time value used by the current control system (see Section 7.1 on page 33 for details). The available range for both parameters is from 0.5 µs to 64 µs. Table 16. Minimum OFF time TOFF_MIN [6 … 0] Time 0 0 0 0 0 0 0 0.5 µs 0 0 0 0 0 0 1 1 µs … … … … … … … … 1 1 1 1 1 1 0 63.
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L6472 9.1.15 Programming manual OCD_TH The OCD_TH register contains the overcurrent threshold value (see Section 6.9 on page 28 for details). The available range is from 375 mA to 6 A, steps of 375 mA, as shown in Table 18. Table 18. Overcurrent detection threshold OCD_TH [3 … 0] 0 0 0 0 375 mA 0 0 0 1 750 mA … … … … … 9.1.16 Overcurrent detection threshold 1 1 1 0 5.625 A 1 1 1 1 6A STEP_MODE The STEP_MODE register has the following structure: Table 19.
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Programming manual L6472 Any attempt to write the register when the motor is running causes the command to be ignored and the NOTPERF_CMD flag to rise (see Section 9.1.19). When when SYNC_EN bit is set low, BUSY/SYNC output is forced low during the commands execution, otherwise, when the SYNC_EN bit is set high, the BUSY/SYNC output provides a clock signal according to the SYNC_SEL parameter. Table 21.
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L6472 9.1.17 Programming manual ALARM_EN The ALARM_EN register allows the selection of which alarm signals are used to generate the FLAG output. If the respective bit of the ALARM_EN register is set high, the alarm condition forces the FLAG pin output down. Table 23. ALARM_EN register 9.1.
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Programming manual L6472 The OSC_SEL and EXT_CLK bits set the system clock source: Table 25.
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L6472 Programming manual Table 27. Overcurrent event OC_SD Overcurrent event 1 Bridges shut down 0 Bridges do not shut down The POW_SR bits set the slew rate value of the power bridge output: Table 28. Programmable power bridge output slew rate values Output slew rate (1) [V/s](1) POW_SR [1 … 0] 0 0 320 0 1 75 1 0 110 1 1 270 1. See SRout_r and SRout_f parameters in Table 5 on page 11 for details. The TQREG bit sets if the torque regulation (see Section 7.
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Programming manual 9.1.19 L6472 STATUS Table 31. STATUS register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 SCK_MOD X X OCD TH_SD TH_WRN UVLO WRONG_CMD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MOT_STATUS DIR SW_EVN SW_F BUSY HiZ NOTPERF_CMD When the HiZ flag is high it indicates that the bridges are in high-impedance state.
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L6472 Programming manual MOT_STATUS indicates the current motor status: Table 33. STATUS register MOT_STATE bits MOT_STATUS Motor status 0 0 Stopped 0 1 Acceleration 1 0 Deceleration 1 1 Constant speed Any attempt to write to the register causes the command to be ignored and the NOTPERF_CMD to rise.
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Programming manual 9.2 L6472 Application commands A summary of commands is given in Table 34. Table 34.
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L6472 9.2.1 Programming manual Command management The host microcontroller can control motor motion and configure the L6472 device through a complete set of commands. All commands are composed by a single byte. After the command byte, some argument bytes should be needed (see Figure 22). Argument length can vary from 1 to 3 bytes. Figure 22. Command with 3-byte argument By default the device returns an all zero response for any received byte, the only exceptions are GetParam and GetStatus commands.
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Programming manual 9.2.2 L6472 Nop Table 35. NOP command structure Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 From host Nothing is performed. 9.2.3 SetParam (PARAM, VALUE) Table 36.
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L6472 Programming manual This command reads the current PARAM register value; PARAM is the respective register address listed in Table 9 on page 40. The command response is the current value of the register (most significant byte first). The number of bytes composing the command response depends on the length of the target register (see Table 9). The returned value is the register one at the moment of GetParam command decoding.
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Programming manual L6472 StepClock command argument and can by changed by a new StepClock command without exiting step-clock mode. Events that cause bridges to be forced into high-impedance state (overtemperature, overcurrent, etc.) do not cause the device to leave step-clock mode. StepClock command does not force the BUSY flag low. This command can only be given when the motor is stopped. If a motion is in progress the motor should be stopped and it is then possible to send a StepClock command.
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L6472 Programming manual This command can only be given when the previous motion command has been completed (BUSY flag released). Any attempt to perform a GoTo command when a previous command is under execution (BUSY low) causes the command to be ignored and the NOTPERF_CMD flag to rise (see Section 9.1.19 on page 52). 9.2.9 GoTo_DIR (DIR, ABS_POS) Table 42.
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Programming manual L6472 If the SW_MODE bit of the CONFIG register is set low, the external switch turn-on event causes a HardStop interrupt instead of the SoftStop one (see Section 6.13 on page 30 and 9.1.18 on page 49). This command keeps the BUSY flag low until the switch turn-on event occurs and the motor is stopped. This command can be given anytime and is immediately executed. 9.2.11 ReleaseSW (ACT, DIR) Table 44.
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L6472 9.2.13 Programming manual GoMark Table 46. GoMark command structure Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 1 1 1 1 0 0 0 From host The GoMark command produces a motion to the MARK position performing the minimum path. Note that this command is equivalent to the “GoTo (MARK)” command. If a motor direction is mandatory the GoTo_DIR command must be used. The GoMark command keeps the BUSY flag low until the MARK position is reached.
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Programming manual 9.2.16 L6472 SoftStop Table 49. SoftStop command structure Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 0 1 1 0 0 0 0 From host The SoftStop command causes an immediate deceleration to zero speed and a consequent motor stop; the deceleration value used is the one stored in the DEC register (see Section 9.1.6 on page 42). When the motor is in high-impedance state, a SoftStop command forces the bridges to exit from high-impedance state; no motion is performed.
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L6472 9.2.19 Programming manual HardHiZ Table 52. HardHiZ command structure Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 0 1 0 1 0 0 0 From host The HardHiZ command immediately disables the power bridges (high-impedance state) and raises the HiZ flag. When the motor is stopped, a HardHiZ command forces the bridges to enter highimpedance state. This command can be given anytime and is immediately executed. This command keeps the BUSY flag low until the motor is stopped. 9.2.
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Package information 10 L6472 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
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L6472 Package information Figure 25.
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Package information L6472 Table 54. HTSSOP28 package mechanical data Dimensions (mm) Symbol Min. Typ. Max. A 1.2 A1 0.15 A2 0.8 b 0.19 0.3 c 0.09 0.2 (1) D 9.6 D1 E E1 (2) 1.0 9.7 6.2 6.4 6.6 4.3 4.4 4.5 2.8 e 0.65 0.45 L1 K 9.8 5.5 E2 L 1.05 0.6 0.75 1.0 0° aaa 8° 0.1 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs do not exceed 0.15 mm per side. 2.
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L6472 Package information Figure 26.
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Package information L6472 Table 55. POWERSO36 package mechanical data Dimensions (mm) Symbol Min. Typ. A a1 3.60 0.10 0.30 a2 3.30 a3 0 0.10 b 0.22 0.38 c 0.23 0.32 D (1) 15.80 16.00 D1 9.40 9.80 E 13.90 14.50 E1 (1) 10.90 11.10 E2 E3 2.90 5.8 6.2 e 0.65 e3 11.05 G 0 0.10 H 15.50 15.90 h L 1.10 0.80 N S 68/70 Max. 1.
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L6472 11 Revision history Revision history Table 56. Document revision history Date Revision 24-Jan-2012 1 Initial release. 2 Changed the title. Changed TOP value in Table 2. Removed Tj parameter in Table 3. Added footnote to Table 9. Changed fast decay time in Table 14. Changed output slew rate values in Table 28 Updated HTSSOP28 package mechanical data. 3 Updated Section 9.1.11 (updated available range for both parameters).
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