Datasheet

Power bridges L6460
62/139 Doc ID 17713 Rev 1
Figure 17. Half bridge configuration
In this case each half bridge will behave according to the following truth table.
Note: When “low power mode” bit is active the bridges will reduce its biasing thus contributing to
the power saving.
When a current limit event occurs this event will be latched and the bridges will remain in
high impedance state for the off time.
Table 19. Half bridge truth table
TSD nReset
Low
power
mode
Enable
Current
limit
MtrXCtrl
SideA/B
PWM OUT
1XXXXXXZ
00XXXXXZ
011XXXXZ
0100XXXZ
0101000Z
01010010
0101010Z
01010111
01011XXZ
High side
Driver
Low side
Driver
Control
Logic
DCX Phase output
V
Supply
V
pump
Control Signals
From SPI
Fault Signals