Datasheet
Electrical specifications L6460
28/139 Doc ID 17713 Rev 1
I
AD
A/D path absorbed current
ADChannelX[4:0]
=10001 and
bit EnDacScale=0
-1 1 µA
t
DELAY
Delay from serial write to pin
low
C
LOAD
=50 pF
(45)
500 ns
SPI interface
(40)
V
IH
High level input voltage
(46)
1.6 V
V
IL
Low level input voltage
(46)
0.8 V
V
HYS
Input voltage hysteresis
(46)
0.15 0.22 V
V
OH
High level output voltage I
OUT
= -10mA,
(47)
2.75 V
V
OL
Low level output voltage I
OUT
= 10mA,
(47)
0.4 V
t
SCLK
SCLK period 62.5 ns
t
SCLK_rise
SCLK rise time 2 ns
t
SCLK_fall
SCLK fall time 2 ns
t
SCLK_high
SCLK high time 20 ns
t
SCLK_low
SCLK low time 20 ns
t
nSS_setup
nSS setup time 10 ns
t
nSS_hold
nSS hold time 10 ns
t
nSS_min
nSS high minimum time 30 ns
t
MOSI_setup
MOSI setup time 10 ns
t
MOSI_hold
MOSI hold time 10 ns
t
MISO_rise
MISO rise time C
LOAD
=50pF
(48)
9ns
t
MISO_fall
MISO fall time C
LOAD
=50pF
(48)
9ns
t
MISO_valid
MISO valid from clock low 0 15 ns
t
MISO_disable
MISO disable time 0 15 ns
C
LOAD
MOSI maximum load 200 pF
1. This value is useful to define the voltage rating for external capacitor to be connected from V
Supply
to V
SupplyInt
.
2. This typical value is only intended to give an estimation of the current consumption when L6460 is configured in simple
regulators mode (see following Chapter 8.6.4) at the end of the start up sequence and with no load on regulators. This
typical value allows a raw choose of the external resistor but the definitive choose must be done according to the
recommendations on Chapter 4.1).
3. Measured between 10% and 90% of output voltage transition.
4. Measured from a fault detection to 50% of output voltage transition.
5. Current is defined to be positive when flowing into the pin.
6. Load regulation is calculated at a fixed junction temperature using short load pulses covering all the load current range. This
is to avoid change on output voltage due to heating effect.
7. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (V
LINmain_FB
).
8. Default state.
9. The regulated voltage can be calculated using the formula: V
SWmain_OUT =
V
FBREF
*(R
a
+R
b
)/R
b
.
Table 5. Electrical characteristics (continued)
Parameter Description Test condition Min Typ Max Unit