Datasheet

Serial interface L6460
130/139 Doc ID 17713 Rev 1
Figure 45. SPI read transaction
23.2 Write transaction
A write transaction (see Figure 46) is always started by the master lowering the signal on
nSS pin. The other bits are then sent on the MOSI pin with this order:
1. 7-bit representing the address of the register that must be written (MSB first [A6…A0]);
2. 2-bit that must be “01” for a read transaction;
3. 2-bit representing L6460 IC address;
4. 1-bit reserved for future use that must be set at “0”.
The data to be written (MSB first D15…D0) are then read from MOSI pin. The length of data
field can be 16 or 20 bits, but only the first 16-bit are accepted as valid data. Data is latched
on rising edge of the nSS line.
Figure 46. SPI write transaction
The SPI input and output timing definitions are shown in the Table 5 on page 17
nSS
A6 A0
D15 D0
Register
Address fiel
d
Data Field
Control
Field
IC
address
Hi
g
hIm
p
edanc
e
SCLK
MOSI
MISO
n
SS
SCLK
MOSI
MISO
A6 A0 D1
5
D0
Register
Address fiel
d
Data Field
Control
Field
IC
addres
Hi
g
h Im
p
edanc
e