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July 2010 Doc ID 17713 Rev 1 1/139

139

L6460

SPI configurable stepper and DC multi motor driver

Features

■ Operating supply voltage from 13 V to 38 V

■ 4 full bridge driver configurable in multi-motor

application to drive:

– 2 DC and 1 stepper motor

–4 DC motor

■ Bridge 1 and 2 (R

DSon

= 0.60 Ω) can be

configured to work as:

– Dual full bridge driver

– Super DC driver

– 2 half bridge driver

– 1 super half bridge

–2 power switches

– 1 super power switch

■ Bridge 3 and 4 (R

DSon

= 0.85 Ω) can be

configured to work as:

– Same as bridges 1 and 2, listed above

– Stepper motor driver: up to 1/16

microstepping

– 2 buck regulators (bridge 3)

– 1 super buck regulator

– Battery charger (bridge 4)

■ Power supply management

– One switching buck regulator

– One switching regulator controller

– One linear regulator

– One battery charger

■ Fully protected through

– Thermal warning and shutdown

– Overcurrent protection

– Undervoltage lock-out

■ SPI interface

■ Programmable watchdog function

■ Integrated power sequencing and supervisory

functions with fault signaling through serial

interface and external reset pin

■ Very low power dissipation in shut-down mode

(~35 mW)

■ Auxiliary features

– Multi-channels 9 bit ADC

– 2 operational amplifiers

– Digital comparator

– 2 low voltage power switches

– 3 general purpose PWM generators

–14 GPIOs

Description

The L6460 is optimized to control and drive multi-

motor system providing a unique level of

integration in term of control, power and auxiliary

features. Thanks to the high configurability L6460

can be customized to drive different motor

architectures and to optimize the number of

embedded features, such as the voltage

regulators, the high precision A/D converter, the

operational amplifier and the voltage

comparators. The possibility to drive

simultaneously stepper and DC motor makes

L6460 the ideal solution for all the application

featuring multi motors.

Table 1. Device summary

Order code Package Packing

L6460

TQFP64

Tray

L6460TR Tape and reel

TQFP64 exposed pad

www.st.com

Summary of content (139 pages)

PAGE 1
L6460 SPI configurable stepper and DC multi motor driver Features ■ Operating supply voltage from 13 V to 38 V ■ 4 full bridge driver configurable in multi-motor application to drive: – 2 DC and 1 stepper motor – 4 DC motor ■ Bridge 1 and 2 (RDSon = 0.60 Ω) can be configured to work as: – Dual full bridge driver – Super DC driver – 2 half bridge driver – 1 super half bridge – 2 power switches – 1 super power switch ■ TQFP64 exposed pad ■ Bridge 3 and 4 (RDSon = 0.
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Contents L6460 Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 L6460’s main features .
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L6460 Contents 8.6.1 Bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.6.2 Primary regulator mode (KP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.6.3 Regulators mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.6.4 Simple regulator mode (KT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.6.5 Bridge + VEXT mode . . . . . . . . . . . . . . . . . .
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Contents L6460 15.1 Voltage divider specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 16 Current DAC circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 17 Operational amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 18 Low voltage power switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 19 General purpose PWM . . . . . . . . . . . . . . . . . . . . . .
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L6460 Contents 24 Registers list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 25 Schematic examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 26 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of tables L6460 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48.
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L6460 Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. List of tables GPIO[9] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 GPIO[10] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 GPIO[11] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of figures L6460 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42.
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L6460 Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. List of figures GPIO[13] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 GPIO[14] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 SPI read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 10
General description L6460 1 General description 1.1 Overview L6460 offers the possibility to control and power multi motor systems, through the management of simultaneous driving of stepper and DC motor. A number of features can be configured through the digital interface (SPI), including 3 voltage regulators, 1 high precision A/D converter, 2 operational amplifiers and 14 configurable GPIOs.
PAGE 11
L6460 Pin connection DC1_PLUS 1 VSWDRV_SNS 2 VSWDRV_FB VSWDRV_SW GPIO6 VGPIO_SPI GPIO7 VSupplyInt 60 59 58 57 56 55 54 N.C. VSWDRV_GATE 61 DC3_PLUS VPump 62 VSupply CPH 63 V3V3 CPL 64 nRESET VSupply Pin connection DC1_PLUS Figure 2. 53 52 51 50 49 48 DC3_SENSE 47 GPIO5 3 46 GPIO9 GPIO4 4 45 GPIO10 GND_PAD GPIO3 5 44 GPIO11 DC1_MINUS 6 43 N.C.
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General description 1.3 Pin list Table 2.
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L6460 General description Table 2. Pins configuration (continued) Pin # Pin name Description Type 35 GPIO12 General purpose I/O Analog In/Out - CMOS bi-dir 36 GPIO13 General purpose I/O Analog In/Out - CMOS bi-dir 37 GPIO14 General purpose I/O Analog In/Out - CMOS bi-dir 38 N.C.
PAGE 14
L6460’s main features 2 L6460 L6460’s main features L6460 includes the following circuits: ● Four widely configurable full bridges: – – ● ● 14/139 Diagonal RDSon: 0.6 Ω typ. – Max operative current = 2.5 A. Bridges 3 and 4: – Diagonal RDSon: 0.85 Ω typ. – Max operative current = 1.5 A. Bridge 1: – DC motor driver. – Super DC (bridge 1 and 2 paralleled form superbridge1). – 2 independent half bridges.
PAGE 15
L6460 L6460’s main features voltages. This regulator can be used to drive an external bipolar pass transistor to generate high current/low ripple output voltages. ● One bidirectional serial interface with address detection so that different ICs can share the same data bus. ● Integrated power sequencing and supervisory functions with fault signaling through serial interface and external reset pin. ● Fourteen general purpose I/Os that can be used to drive/read internal/external analog/logic signals.
PAGE 16
Electrical specifications L6460 3 Electrical specifications 3.1 Absolute maximum rating The following specifications define the maximum range of voltages or currents for L6460. Stresses above these absolute maximum specifications may cause permanent damage to the device. Exposure to absolute maximum ratings for extended periods may affect device reliability. Table 3.
PAGE 17
L6460 Electrical specifications Table 4. IC operating ratings Parameter Description VSWDRV_GATE Gate drive pin voltage VSWDRV_SNS Sense pin voltage TJ Junction temperature Test condition Operating Min Max Unit 0 VPump V VSupply VSupply -3V V -40 125 °C 1. For Vsupply lower than 21 V an external resistor between Vsupply and Vsupply Int pins are required. For Vsupply lower than 15 V external diodes for charge pump are required. 2.
PAGE 18
Electrical specifications Table 5. L6460 Electrical characteristics (continued) Parameter Description Test condition tnRST_fall nRESET fall time I=1mA C=50pF(3) tnRST_del nRESET delay time (4) Min Typ Max Unit 15 ns 150 ns VSupply_UV_f VSupply falling threshold 10.2 11 11.8 V VSupply_UV_r VSupply rising threshold 10.5 11.5 12.5 V VSupply hysteresis 0.3 0.5 0.7 V VSupply_UV_hys tSupply_UV VSupply UV filter time VS_Int_UV_f VSupplyInt falling threshold 9.7 10.7 11.
PAGE 19
L6460 Electrical specifications Table 5. Electrical characteristics (continued) Parameter Description VIH nAWAKE high logic level voltage VHYS nAWAKE input hysteresis IOUT nAWAKE pin output current IINP tAWAKEFILT Test condition Min Typ Max 1.6 V 0.25 nAWAKE=0V(5) nAWAKE pin input current nAWAKE=0.8V (5) Unit V -0.72 -2 mA 0.2 0.4 mA Filter time μs 1.
PAGE 20
Electrical specifications Table 5. L6460 Electrical characteristics (continued) Parameter Vloop Description Test condition Min Loop voltage accuracy Typ Max Unit ±3% VSW_UV_f Under voltage falling threshold (10) 84.5 87 89.5 % VSW_UV_r (10) 90.5 93 95.5 % VSW_UV_hys tprim_uv Ilimit tdeglitch Under voltage rising threshold Under voltage hysteresis 6 % Under voltage deglitch filter 5 µs 5 3.
PAGE 21
L6460 Electrical specifications Table 5. Electrical characteristics (continued) Parameter Description Test condition VSWD_UV_f Under voltage falling threshold (14) VSWD_UV_r Under voltage rising threshold (14) VSWD_UV_hys tprim_uv Vovc tdeglitch tI_lim tI_limUV FSWD_PWM Min Typ Max Unit 84.5 87 89.5 % 90.5 93 95.
PAGE 22
Electrical specifications Table 5.
PAGE 23
L6460 Electrical specifications Table 5. Electrical characteristics (continued) Parameter Description Test condition Min Typ Max Unit 0.776 0.8 0.824 V 0.97 1 1.03 V 2.425 2.5 2.575 V SelFBRef = ‘11’ 2.91 3 3.09 V GPIO feedback pin current Tjunction = 125°C 0V≤Feedback ≤ 3V -15 15 µA Vout Output voltage range VSupply = 36V(23) 0.8 30 V Iload Output load current VSupply = 36V 0.002 1.5 A Internal high/low side RDSon Tjunction = 125°C; Iload=1A 0.
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Electrical specifications Table 5. L6460 Electrical characteristics (continued) Parameter Description Test condition Min Typ Max Unit 0.873 0.9 0.927 V SelCurrRef = ‘01’ 1.394 1.437 1.48 V SelCurrRef = ‘10’ 1.746 1.8 1.854 V SelCurrRef = ‘11’ 2.182 2.25 2.318 V (27) 1.412 30 V 0.002 3 A 0.
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L6460 Electrical specifications Table 5.
PAGE 26
Electrical specifications Table 5. L6460 Electrical characteristics (continued) Parameter VOp1PlusRef VOp2PlusRef Avd Description Test condition Operational amplifier 1 and 2 reference voltage OpxRef[1:0]=00 OpxRef[1:0]=01 OpxRef[1:0]=10 OpxRef[1:0]=11 Open loop gain VICM=1.65V ILOAD= 0mA Min Typ Max Unit 0.97 1.6 1.94 2.425 1 1.65 2 2.5 1.03 1.7 2.06 2.
PAGE 27
L6460 Electrical specifications Table 5. Electrical characteristics (continued) Parameter tI_lim CLOAD Description Test condition Min Typ Max Unit Current limit response time 650 ns Max load capacitance 2.5 µF tON Turn on propagation delay VGPIO_SPI=3.3V ILOAD=1mA CLOAD=100pF(44) 450 650 ns tOFF Turn off propagation delay VGPIO_SPI=3.
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Electrical specifications Table 5. L6460 Electrical characteristics (continued) Parameter Description Test condition A/D path absorbed current ADChannelX[4:0] =10001 and bit EnDacScale=0 Delay from serial write to pin low CLOAD =50 pF(45) VIH High level input voltage (46) VIL Low level input voltage (46) Input voltage hysteresis (46) IAD tDELAY Min Typ Max Unit 1 µA 500 ns -1 SPI interface (40) VHYS VOH VOL tSCLK High level output voltage Low level output voltage 1.6 V 0.
PAGE 29
L6460 Electrical specifications 10. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (VSW_main_FB). 11. This condition is intended to simulate an extra current on output. 12. This condition is intended to simulate a short circuit on output. 13. Rise and fall time are measured between 10% and 90% VSWmain output voltage. 14. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (VSWDRV_FB). 15.
PAGE 30
Internal supplies 4 L6460 Internal supplies L6460 includes three internal regulators used to provide a regulated voltage to internal circuits. The internal regulators are the following: - VSupplyInt regulator. - Charge pump regulator. - V3v3 regulator. 4.1 VSupplyInt regulator VSupplyInt is the output of an internal regulator used to supply some internal circuits. This regulator is not intended to provide external current so it must not be used to supply external loads.
PAGE 31
L6460 4.2 Internal supplies Charge pump regulator L6460 implements a charge pump regulator to generate a voltage over VSupply.This voltage is used to drive internal circuits and the external FET driver and cannot be used for any other purpose. This circuit is always under the supervisory circuit control, so no regulator can start before the VPump voltage reaches its undervoltage rising threshold.
PAGE 32
Supervisory system 5 L6460 Supervisory system The supervisory circuitry monitors the state of several functions inside L6460 and resets the device (and other ICs if connected to nRESET pin) when the monitored functions are outside their normal range. Supervisory circuitry can be divided into three main blocks: – Power on reset (POR) generation circuitry. – nRESET (nRST_int) generation circuitry. – Thermal shut down (TSD) generation circuitry.
PAGE 33
L6460 Supervisory system state. This stretch time can be selected by setting the ID[1:0] bits in the SampleID register according to following table. Table 6. Stretch time selection Selected stretch time ID[1] ID[0] Note Typ 0 0 16ms 0 1 32ms 1 0 48ms 1 1 64ms Default state When nRST_int becomes active (logic level = “0”) it sets in their reset state some of the functions inside L6460.
PAGE 34
Supervisory system L6460 Figure 5.
PAGE 35
L6460 5.3 Supervisory system Thermal shut down generation circuit The third component of the supervisory circuit is the thermal shut down generation circuit. This circuit generates two different flags depending on the IC temperature: – the “TSD” flag indicates that the IC temperature is greater than the maximum allowable temperature.
PAGE 36
Watchdog circuit 6 L6460 Watchdog circuit The Watchdog timer can be used to reset L6460 if it is not serviced by the firmware that can periodically write at logic level “1’ the ClrWDog bit in the WatchDogStatus register. This circuit is disabled by default; firmware can enable it by setting at logic level ‘1’ the WDEnable bit in the WatchDogCfg register.
PAGE 37
L6460 Watchdog circuit Table 7.
PAGE 38
Internal clock oscillator 7 L6460 Internal clock oscillator L6460 includes a free running oscillator that does not require any external components. This circuit is used to generate the time base needed to generate the internal timings; the typical frequency is 16 MHz. The oscillator circuit starts as soon as the IC exits from the power on reset condition and it is stopped only when in “low power mode”.
PAGE 39
L6460 8 Start-up configurations Start-up configurations L6460 start-up configuration is selected by setting in different states the GPIO[0], GPIO[3] and GPIO[4] pins. Each of these is a three state input pin and is able to distinguish among the following situations: Table 8. Possible start-up pins state symbol Pin condition State symbol Shorted to ground 0 Shorted to V3v3 pin 1 Floating Z Note: “Shorted” means: R≤1KOhm; “Z” means: R≥10KOhm, C≤200pF 8.
PAGE 40
Start-up configurations Table 9.
PAGE 41
L6460 8.3 Start-up configurations Slave device mode In slave device mode, L6460 consider the nAWAKE pin as an input enable. Since this is now a digital pin, the current pull up source inside the nAWAKE circuit is disabled. At the startup, if the nAWAKE pin is found to be low for a period higher than tAWAKEFILT, L6460 enters directly in the “Low Power mode”; when nAWAKE pin is pulled high for a period higher than tAWAKEFILT, L6460 begins its start up procedure. 8.
PAGE 42
Start-up configurations 8.6.2 L6460 Primary regulator mode (KP) In this configuration bridge 4 can be configured by firmware while bridge 3 is configured as two separate synchronous switching regulators. The last regulator in the sequence (VAUX2_SW) is not considered a system regulator. When in this mode the power-up sequence is: 8.6.3 1. Auxiliary switching regulator1 (VAUX1_SW). 2. Main switching regulator (VSWmain) together with main linear regulator (VLINmain). 3.
PAGE 43
L6460 8.6.6 Start-up configurations Secondary regulators mode In this configuration, bridge 3 is configured as a single synchronous switching regulator using its two half bridges in parallel (VAUX_(1//2)SW). When in this mode the power-up sequence is: 1. Main switching regulator (VSWmain). 2. Auxiliary switching regulator (VAUX(1//2)_SW). 3. Main linear regulator (VLINmain).
PAGE 44
Power sequencing 9 L6460 Power sequencing As soon as VSupply and VSupplyInt are above their power on reset level, L6460 will start the charge pump circuit; once VPump voltage reaches its under voltage rising threshold, L6460 begins a sequence that starts the regulators considered system regulators. A regulator is considered a System regulator if: – It has to start in on state without any user action. – It is included in the power-up sequence.
PAGE 45
L6460 10 Power saving modes Power saving modes Saving power is very important for today platforms: L6460 implements different functions to achieve different levels of power saving. Sections here below describe these different power saving modes. Standby mode Almost all low voltage circuitry inside L6460 are powered by V3v3 internal regulator; this regulator is a linear regulator powered by VSupplyInt.
PAGE 46
Power saving modes 10.2 L6460 Hibernate mode L6460’s hibernate mode allows the firmware to switch off some (or all) selected System Regulators leaving in on state only those necessary to resume L6460 to operative condition when waked-up by an external signal. Hibernate mode is selected when the firmware writes the command word in the HibernateCmd register.
PAGE 47
L6460 Power saving modes If L6460 is not configured as slave device a current source IOUT will be active on this pin, while the current sink IINP will be disabled. If L6460 is configured as a Slave device, the current sink IINP will be active until nAWAKE pin is detected high for the first time; after that both current sources IINP and IOUT will be disabled and the nAWAKE pin can be considered as a digital input. Here below is reported the nAWAKE pin simplified schematic. Figure 8.
PAGE 48
Linear main regulator 11 L6460 Linear main regulator The linear main regulator is directly powered by VSupply voltage and it is one of the regulators that L6460 could consider as a system regulator. This means that the voltage generated by this regulator is not used to power any internal circuit, but L6460 will check that the feedback voltage VLINmain_FB is in the good value range before enabling all its internal functions.
PAGE 49
L6460 Linear main regulator Figure 10. Linear main regulator with external bipolar for high current V supply Body Diode Driver VLINmain_OUT Cload + Ra VLINmain_FB - VLINmain_Ref Rb Whichever configuration is used (regulator or controller), a ceramic capacitor must be connected on the output pin towards ground to guarantee the stability of the regulator; the value of this capacitance is in the range of 100 nF to 1 µF depending on the regulated voltage; ● VLINmain_OUT = 0.8 V --> 1 µF ● 0.
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Main switching regulator 12 L6460 Main switching regulator Main switching regulator is an asynchronous switching regulator intended to be the source of the main voltage in the system. It implements a soft start strategy and could be a system regulator so even if its output voltage VSWmain is not used to power any internal circuit, L6460 will check that it is in the good value range before enabling all its internal functions.
PAGE 51
L6460 Main switching regulator Figure 11. Main switching regulator functional blocks VSupply Current Sense Charge pump Voltage High Side Driver VSWmain_SW La Ra C Voltage Loop Control Control Logic From Central Logic + VSWmain_FB Rb Regulator Freq Regulator Ref Under voltage flag Filter To Central Logic + Under voltage Threshold In pulse skipping control the duty cycle must be chosen by the user depending on supply voltage and output regulated voltage.
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Switching regulator controller 13 L6460 Switching regulator controller This circuit controls an external FET to implement a switching buck regulator using a non linear pulse skipping control with internally generated PWM signal. The output voltage will be externally set by a divider network connected on feedback pin.
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L6460 Switching regulator controller Figure 12. Switching regulator controller functional blocks V supply Rsense CurrentSense V SWDRW_sns Charge pump Voltage N-CH Fet Driver V SWDRV_gate V SWDRV La Ra SW V out Voltage C Loop Control Control Logic From Central Logic + SelFBRef[1:0] V SWDRV FB Regulator Freq Rb Analog Mux Vref = 3 V Vref = 3V Vref=0.8V VFBRef Vref=0.8V undervoltage flag + Filter To Central Logic Analog Mux SelFBRef Uv Threshold 1 Uv Threshold 2 13.
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Switching regulator controller 13.2 L6460 Output equivalent circuit The switching regulator controller output driving stage can be represented with an equivalent circuit as in the Figure 13: Figure 13.
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L6460 Switching regulator controller An example of application can be considered the following, supposing the external mosfet type STD12NF06L: – Max DC current load = 3 A – Typ Over current threshold = 3 A * 1.5 = 4.5 A – L = 150 µH – C = 220-330 µF In this conditions the step-down regulator will result over-load protected, short-circuit protected over all the regulated voltage range and the VSupply range. Other application configurations could be evaluated before being implemented.
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Power bridges 14 L6460 Power bridges L6460 includes four H bridge power outputs (each one made by two independent half bridges) that are configurable in several different configurations. Each half bridge is protected against: over-current, over-temperature and short circuit to ground, to supply or across the load. When an over current event occurs, all outputs are turned off (after a filter time), and the over current bit is stored in the internal status register that can be read through SPI.
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L6460 Power bridges Table 14. PWM selection truth table for bridge 1 or 2 Selected PWM(1) MtrXSelPWMSideY [1] MtrXSelPWMSideY [0] 0 0 MotorXPWM (Configurable by means of MtrXCfg register). 0 1 AuxXPWM (Configurable by means of AuxPwmXCtrl register). 1 0 ExtPWM1 (from GPIO 9 input) 1 1 ExtPWM2 (from GPIO 10 input) 1. In this table X stands for 1 or 2, Y stands for A or B. Table 15.
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Power bridges L6460 Figure 15.
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L6460 14.1 Power bridges Possible configurations The selection of the bridge configuration is done through SPI, by writing the MtrXTable[1:0] bits in the MtrXCfg register. The table below shows the correspondence between MtrXTable[1:0] bits and the bridge configuration. Table 16.
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Power bridges 14.1.1 L6460 Full bridge When in full bridge configuration, the drivers will behave according to the following truth table: Table 18.
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L6460 14.1.2 Power bridges Parallel configuration (super bridge) Bridges 1, 2, 3 and 4 can be configured to be used two by two (1 plus 2, 3 plus 4) as one super bridge thus enabling the driving of loads (motors) requiring high currents. In this configuration the half bridges will be paralleled and will work as one phase of the superbridge just created: the two phases + will become phase + of the newly created superbridge while the two phases - will become phase –. Figure 16.
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Power bridges L6460 Figure 17. Half bridge configuration V Supply V pump High side Driver DCX Phase output Control Signals Control Logic Low side Driver Signals Fault From SPI In this case each half bridge will behave according to the following truth table. Table 19.
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L6460 14.1.4 Power bridges Switch configuration Each bridge can be configured to be used as 2 independent switches that connects the output to supply or to ground. It is also possible to parallel the two switches and use them as a single super switch. All resulting switches will behave according to the following truth table. Table 20.
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Power bridges L6460 side power MOS for the whole off time. In fast decay mode the current is recirculated through the high and low side power MOS opposite respect to those forcing current to increase. Mixed decay mode is a selectable mix of the previous two modes (fast decay followed by slow decay) and allows the user to find the best trade off between load current ripple and fast current levels transition.
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L6460 Power bridges Figure 18. Bipolar stepper configuration DC3_PHDC3SENSE V supply DC3_PH+ Stepper Motor VRefA DC4 PH- Supply PH- Supply PH+ PH- PH+ DC4 PH+ Sense Sense Bridge Driver - Control Logic - Toff generation - DAC reference selection Bridge Driver VRefB Ref1 V STEPREF Ref2 DC4SENSE VRefA StepperDACPhA SelStepRef StepperDACPhB VRefB Using the StepCtrlMode[2:0] bits in StepCfg1 register, L6460 can be programmed to internally generate the stepping levels.
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Power bridges L6460 Table 21. Sequencer driver StepFromGpio Sequencer driver 0 StepCmd bit in StepCmd register. 1 GPIO12 input pin. The allowable control modes are as follows: 1. Stepping sequence left to external microcontroller: in this mode the current level in each motor winding is set by the microcontroller via the serial interface. 2. Full step: in this mode the electrical angle will change by 90° steps at each StepReq signal transition.
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L6460 Power bridges Table 23. Note: Stepper sequencer direction StepDir Direction 0 Counter clockwise (CCW) 1 Clockwise (CW) It is intended as clockwise the sequence that forces a clockwise rotation of the versors representing the current module and phase.
PAGE 68
Power bridges L6460 An internal DAC is used to digitally control the output regulated current. The available values are chosen to provide a quasi sinusoidal profile of the current. The current limit in each phase is decided by PhADAC[3:0] bits for phase A and PhBDAC[3:0] bits for phase B. The table below describes the relation between the value programmed in the stepper DAC and the current level. Table 24.
PAGE 69
L6460 Power bridges Table 25. Internal sequencer Typical output current (% of IMAX) Control mode Half step Full step (2 phases on) 1 1 Full step (1 phase on) 1/4 step 1/8 step 1/16 step Phase A (sin) Phase B (cos) Electrical degrees 1 1 1 70.7 70.7 45° 2 77.3 63.4 50.6° 3 83.1 55.6 56.2° 4 88.2 47.1 61.9° 5 92.4 38.3 67.5° 6 95.7 29.0 73.1° 7 98.1 19.5 78.8° 8 100 9.8 84.4° 9 100 HiZ 90° 10 100 -9.8 95.6° 11 98.1 -19.5 101.2° 12 95.7 -29.0 106.
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Power bridges L6460 Table 25. Internal sequencer (continued) Typical output current (% of IMAX) Control mode Half step Full step (2 phases on) Full step (1 phase on) 1/4 step 1/8 step 3 5 9 17 18 10 19 20 6 3 11 21 22 12 23 24 7 4 13 25 26 14 27 28 8 4 15 29 30 16 70/139 31 Doc ID 17713 Rev 1 Resulting electrical angle 1/16 step Phase A (sin) Phase B (cos) Electrical degrees 32 -63.4 -77.3 219.4° 33 -70.7 -70.7 225° 34 -77.3 -63.4 230.6° 35 -83.
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L6460 Power bridges Table 25. Internal sequencer (continued) Half step Full step (2 phases on) Full step (1 phase on) 1/4 step Resulting electrical angle Typical output current (% of IMAX) Control mode 1/8 step 1/16 step Phase A (sin) Phase B (cos) Electrical degrees 32 63 55.6 83.1 33.8° 64 63.4 77.3 39.4° The voltage spikes on Rsense could be filtered by selecting an appropriate blanking time on the output of current sense comparator.
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Power bridges Table 26. L6460 Stepper off time (continued) Off time StepOffTime[4:0] Unit Typ 10100 42 µs 10101 44 µs 10110 46 µs 10111 48 µs 11000 50 µs 11001 52 µs 11010 54 µs 11011 56 µs 11100 58 µs 11101 60 µs 11110 62 µs 11111 64 µs By means of MixDecPhA[4:0] and MixDecPhB[4:0] in StepCfg2 register, the percentage of off time during which each phase will stay in fast decay mode could be programmed according to Table 28.
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L6460 Power bridges Table 27. Stepper fast decay MixDecPhX[4:0] Fast decay percentage during off time Unit Typ 14.1.6 00000 0 % 00001 6.25 % 00010 12.5 % 00011 18.75 % 00100 25 % 00101 31.25 % 00110 37.6 % 00111 43.75 % 01000 50 % 01001 56.25 % 01010 62.5 % 01011 68.75 % 01100 75 % 01101 81.25 % 01110 87.5 % 01111 93.
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Power bridges L6460 Here after are summarized the primary features of the regulator(s): – Synchronous rectification – Automatic low side disabling when current in the inductance reaches 0 to optimize efficiency at low load – Pulse skipping control – Internally generated PWM – Cycle by cycle current limiting using internal current sensor – Protected against load short circuit – Soft start circuitry – Under voltage signal (both continuous and latched) accessible through serial interface.
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L6460 Power bridges voltage thresholds) using serial interface. The feedback reference voltage is selected by writing the SelFBRef[1:0] bits in the Aux1SwCfg or Aux2SwCfg registers. The switching regulators have four possible PWM duty cycles that can be changed using SPI according to Table 28. Table 28.
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Power bridges 14.1.8 L6460 Battery charger or switching regulator (Bridge 4) The functionality of this circuit is obtained by using the bridge 4 output stage. This circuit is powered directly from VSupply and it is intended to be used as a battery charger or a switching regulator. The control loop block diagram is shown in the Figure 21. Figure 21.
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L6460 Power bridges the regulated current: the voltage provided at the IREF_FB pin will be compared to the internal reference. L6460 has the possibility to choose between four voltage references using the serial interface, writing the SelCurrRef[1:0] bits in the Aux3SwCfg1 register. Regardless of the CurrRef voltage, if the IREF_FB pin remains below the chosen threshold, the internal current limitation will work (typical Ilimit current 4A).
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Power bridges L6460 Figure 23. Simple buck regulator L6460 IREF_FB COMP_I VREF_FB COMP_V PULSE SKIPPING BURST CONTROL LOGIC PEAK CURRENT MODE CONTROL LOGIC DC4_plus PWM Ilimit BRIDGE 4 PARALLELED POWER STAGE TO LOAD DC4_minus FBRef SelFBRef<1:0> CurrRef SelCurrRef<1:0> When this control loop is intended to be used as a simple buck regulator, the proper Aux3BatteryCharge bit must be written in the Aux3SwCfg1 register. The regulator will also implement a soft start strategy.
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L6460 Power bridges Table 29.
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AD converter 15 L6460 AD converter L6460 integrates and makes accessible via SPI a general purpose multi-input channel 3.3V analog to digital converter (ADC). The ADC can be configured to be used as: ● 8-bit resolution ADC. ● 9-bit resolution ADC. The result of the conversion will always be a 9-bit word; the difference between the two configurations is that, to speed up the conversion, the resolution is reduced when the ADC is used in the 8-bit resolution mode.
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L6460 AD converter Analog Mux V supply V pump Sample Time 1 Sample Time 0 Figure 24. A2D block diagram V3v3 VLINmain FB VSWmain FB VSWDRV_F B S&H GPIO[0:14] RefOpAmpX OutStripStepperPHX Current DAC Conversion Address 1 A2DType 1 A2DType 0 Conversion Done 0 Conversion Done 1 Conversion Result A2DEnable Conversion Address 0 Selected A2DType A2D Temp Sensors To SPI The A2D system is enabled by setting the A2DEnable bit to ‘1’ in the A2DControl register.
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AD converter Table 31. L6460 Channel addresses A2DChannelX[4:0] (bin.) Converted channel Note 00000 VSupply scaled See voltage divider specification. 00001 VSupplyInt scaled See voltage divider specification. 00010 Vref_2_5V 00011 Temp Sensor1 Temperature sensor1 00100 Temp Sensor2 Temperature sensor2 00101 V3v3 scaled See voltage divider specification.
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L6460 AD converter Table 32. ADC sample times when working as a 8-bit ADC Sample time A2DSampleX[2:0] (binary) Table 33.
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AD converter 15.1 L6460 Voltage divider specifications As can be seen in the A2D block diagram, in order to report some voltages in the A2D working range, they are scaled with a resistor divider before the conversion. Here below are reported the resistor voltage divider specifications: Table 34.
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L6460 16 Current DAC circuit Current DAC circuit L6460 includes a multiple range 6-bit current sink DAC. The LSB value of this DAC can be selected using the DacRange[1:0] bits in the CurrDacCtrl register. The output of this circuit is connected to GPIO[8] that is a 5 V tolerant pin. The value of this pin can be converted using ADC. The pin value can be scaled before being converted by enabling the internal resistor divider connected to this pin.
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Current DAC circuit L6460 The current DAC has three possible current ranges that can be selected using the DacRange[1:0] bits in the CurrDacCtrl register. The DAC range selection table is shown in Table 35. Table 35. Current DAC truth table DacRange[1] DacRange[0] LSB typical current ILSB typ Full scale typical current IFULL typ 0 0 Disabled Disabled 0 1 10 µA 0.63 mA 1 0 100 µA 6.
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L6460 17 Operational amplifiers Operational amplifiers L6460 contains two rail to rail output, high bandwidth internally compensated operational amplifiers supplied by VGPIO_SPI pin. The operative supply range is 3.3 V ± 4.5% Each operational amplifier can have all pin accessible or, to save pins, can be internally configured as a buffer.
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Operational amplifiers L6460 The operational amplifiers are capable to drive a capacitive load in buffer configuration up to a maximum of 100 pF; for higher capacitance it is necessary to add resistive loads to increase the OP output current, and/or to add a low resistor (10 Ω) in series to the load capacitance. To use the operational amplifiers as comparators the user must disable internal compensation writing a logic one in the OpXDisComp bit in the OpAmpXCtrl register.
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L6460 Low voltage power switches Low voltage power switches are analog switches designed to operate from a single +2.4 V to +3.6 V VGPIO_SPI supply. They are intended to provide and remove power supply to low voltage devices. When switched on, they connect the VGPIO_SPI pin to their output pin (GPIO[6] for low voltage power switch 1 or GPIO[7] for low voltage power switch 2) thus powering the device connected to it. The turning on and off of each switch can be controlled through serial interface.
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General purpose PWM 19 L6460 General purpose PWM L6460 includes three general purpose PWM generators that can be redirected on GPIO pins (see Chapter 22). Two of these generators (Aux_PWM_1 and Aux_PWM_2) work with a fixed period FOSC/512 and have a programmable duty cycle; the other one (GP_PWM) has a programmable base time clock and a programmable time for both high and low levels. 19.
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L6460 Interrupt controller L6460 contains one programmable interrupt controller that can be used to advice the firmware, through the serial interface, when a certain event happens inside the IC. The output of the interrupt circuit can be also redirected on a GPIO pin therefore the event can be signaled directly to the external circuits. Figure 28.
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Interrupt controller L6460 Table 36. Interrupt controller event (continued) Event WDWarn WD DigCmp Event description Notes Watch dog warning event Watch dog event Digital comparator ADCDone1 ADC conversion done 1 (1) ADCDone2 ADC conversion done 2 (1) Vloop1Ilim AUX1 Ilimit event. 1. This event is disabled if the related ADC channel is configured in continuous mode.
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L6460 21 Digital comparator Digital comparator L6460 includes one digital comparator that can be used to signal, through serial interface, that a channel converted by the ADC is greater, greater-equal, lesser, lesser equal, or equal than a fixed value set by serial interface or than the value converted by the other ADC channel.
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Digital comparator L6460 Figure 29. Digital comparator block diagram DigCmpValue[9:0] ADC FSM Update Signal A2DDone1 Logic ‘1’ A2DDone0 DigCmpSelCh0[1] DigCmpUpdate[1:0] A2DResult0[8:0] Three check s filter A2DResult1[8:0] DigCmpSelCh0[0] CmpOut Data0[9:0] DigCmpSelCh1[0] COMPARATOR SelCmpType[1:0] EnDigCmp Data1 [9:0] DigCmpSelCh1[1] In Table 37 is reported the comparison type truth table. Table 37.
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L6460 22 GPIO pins GPIO pins Some of the pins of L6460 are indicated as GPIO (General purpose I/O). These pins can be configured to be used in different ways depending on customer application. All GPIOs can be used as digital input/output pins with digital value settable/readable using serial interface or as analog input pins that can be converted using the A2D system. Some of the pins can be used for special purposes: i.e.
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GPIO pins Table 39.
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L6460 GPIO pins Table 40. Abbreviations Abbreviation ADC input Meaning Input to the ADC system. SPI IN Digital state of this pin is readable through SPI. SPI OUT Digital state of this pin can be set through SPI. BB Back to back high side driver. Comp1 IN - This pin can be used as minus input for comparator 1. Comp2 IN - This pin can be used as minus input for comparator 2. Vaux1 FB This pin can be used as feedback input for AUX1 regulator obtained by using bridge 3.
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GPIO pins L6460 Table 40. Abbreviations (continued) Abbreviation OpAmp2 Out Meaning This pin can be used as operational amplifier 2 output. ID 1 This pin is used to determine the SPI ID1 bit value. ID 2 This pin is used to determine the SPI ID2 bit value. Slave Control This pin is used as slave control when the IC is configured as master. Hereafter are reported the detailed specifications for each GPIO.
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L6460 22.1 GPIO pins GPIO[0] The GPIO[0] truth table is (for the abbreviation list please refer to Table 40). Table 41.
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GPIO pins L6460 Figure 30.
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L6460 22.2 GPIO pins GPIO[1] The GPIO[1] truth table is (for the abbreviation list please refer to Table 40). Table 42.
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GPIO pins L6460 Figure 31.
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L6460 22.3 GPIO pins GPIO[2] The GPIO[2] truth table is (for the abbreviation list please refer to Table 40). Table 43.
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GPIO pins L6460 Figure 32.
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L6460 22.4 GPIO pins GPIO[3] The GPIO[3] truth table is (for the abbreviation list please refer to Table 40). Table 44.
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GPIO pins L6460 Figure 33.
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L6460 22.5 GPIO pins GPIO[4] The GPIO[4] truth table is (for the abbreviation list please refer to Table 40). Table 45.
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GPIO pins L6460 Figure 34.
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L6460 22.6 GPIO pins GPIO[5] The GPIO[5] truth table is (for the abbreviation list please refer to Table 40). Table 46.
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GPIO pins L6460 Figure 35.
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L6460 22.7 GPIO pins GPIO[6] The GPIO[6] truth table is (for the abbreviation list please refer to Table 40): Table 47. GPIO[6] truth table GPIO[6] SPI BITS StdByMode AEnLow VSw[1] GpioOut Mode[2] Mode[1] Mode[0] enable[6] Function Note 1 X X X X X Low Volt. Pow. Sw. 1 0 1 X X X X Low Volt. Pow. Sw.
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GPIO pins L6460 Figure 36.
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L6460 22.8 GPIO pins GPIO[7] The GPIO[7] truth table is (for the abbreviation list please refer to Table 40). Table 48. GPIO[7] truth table GPIO[7] SPI BITS EnLowVSw[2] GpioOut enable[7] Function Note (1) Mode[2] Mode[1] Mode[0] 1 X X X X Low Volt. Pow. Sw.
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GPIO pins L6460 Figure 37.
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L6460 22.9 GPIO pins GPIO[8] The GPIO[8] truth table is (for the abbreviation list please refer to Table 40). Table 49.
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GPIO pins L6460 Figure 38.
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L6460 22.10 GPIO pins GPIO[9] The GPIO[9] truth table is (for the abbreviation list please refer to Table 40). Table 50.
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GPIO pins L6460 Figure 39.
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L6460 22.11 GPIO pins GPIO[10] The GPIO[10] truth table is (for the abbreviation list please refer to Table 40). Table 51.
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GPIO pins L6460 Figure 40.
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L6460 22.12 GPIO pins GPIO[11] The GPIO[11] truth table is (for the abbreviation list please refer to Table 40). Table 52.
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GPIO pins L6460 Figure 41.
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L6460 22.13 GPIO pins GPIO[12] The GPIO[12] truth table is (for the abbreviation list please refer to Table 40. Table 53.
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GPIO pins L6460 Figure 42.
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L6460 22.14 GPIO pins GPIO[13] The GPIO[13] truth table is (for the abbreviation list please refer to Table 40). Table 54.
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GPIO pins L6460 Figure 43.
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L6460 22.15 GPIO pins GPIO[14] The GPIO[14] truth table is (for the abbreviation list please refer to Table 40). Table 55.
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GPIO pins L6460 Figure 44.
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L6460 23 Serial interface Serial interface L6460 can communicate with an external microprocessor by using an integrated slave SPI (serial protocol interface). Through this interface almost all L6460 functionalities can be controlled and all the ICs can be seen as a register map made by 128 register of 16-bit each.
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Serial interface L6460 Figure 45. SPI read transaction nSS SCLK Register Address field MOSI A6 Data Field A0 High Impedance MISO 23.2 Control IC Field address D15 D0 Write transaction A write transaction (see Figure 46) is always started by the master lowering the signal on nSS pin. The other bits are then sent on the MOSI pin with this order: 1. 7-bit representing the address of the register that must be written (MSB first [A6…A0]); 2. 2-bit that must be “01” for a read transaction; 3.
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L6460 Serial interface Figure 47. SPI input timing diagram T nss T sclk setup T nss period hold T nss min V IH V IL nSS T sclk T sclk hig low SCLK V IH V IL MOSI V IH V IL T mosi T mosi setup hold T sclk rise T sclk fall Figure 48.
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Registers list 24 L6460 Registers list Many of the L6460 functionalities are controlled or can be supervised by accessing to the relative register through serial interface. All these registers can be seen from the user (microcontroller) point of view as a register table. Each register is one word wide (16-bit) and can be read using a 7-bit address Table 56.
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L6460 Registers list Table 56.
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Registers list L6460 Table 56.
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nRESET JP7 1 2 3 2 JP1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 LED SCLK D2 R39 Open 330 LED 1 RESET AWAKE R3 R11 R41 1K R40 560 R10 4.7K R13 1 2 LED D1 D5 Gpio5 nSS MISO MOSI J7 VSWMAIN GND 3.3V 2.5A 4.7K R2 nSS 100nF C29 1 Master 4.7K R1 Q3 BC846B CON17X2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 J10 nRESET MISO MOSI SCLK Slave Vsupply nAWAKE J8 CON5X2 1 2 3 4 5 6 7 8 9 10 J1 VLINMAIN GND 1.2V 0.5A nSS 1 2 3 2 4.
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BATTERY + GND 12V 1.5A max D3 BZX284C15 1 2 C32 100pF C22 22uF 16V J10 + 1 R14 4.7K 1W R24 10K R19 10K C23 100nF J8 +Vop Q4 BSP51 1 R15 1K R11 560 R45 1K R48 330 1 Q9 R44 2.2K BC857B 1 GREEN330 LED 1 R38 4.7K R37 ES3B J5 1 2 Q2 BSP51 - + 0.1 1W R25 150K 0.1% R28 150K 0.1% C5 10pF R23 10K 0.1% R20 10K 0.1% R17 C19 10uF 10V R7 1K R5 2.2K 2 3 U2A LM358 + +3_3VS C18 330nF VSWMAIN GND 3.
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L6460 26 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Figure 51. TQFP64 mechanical data an package dimensions mm inch DIM. MIN. TYP. A MAX. MIN. TYP. 1.20 A1 0.05 A2 0.95 b 0.17 MAX. 0.0472 0.15 0.002 1.
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Revision history 27 L6460 Revision history Table 57. 138/139 Document revision history Date Revision 02-Jul-2010 1 Changes Initial release.
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L6460 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.