Datasheet

ManualsBrandsSTMICROELECTRONICS ManualsDiodesTVS Diode

July 2007 Rev 1 1/11

ESDAULC6-3BP6

ESDAULC6-3BF2

ESD protection for high speed interface

Main applications

Where transient overvoltage protection in ESD

sensitive equipment is required, such as:

■ Computers

■ Printers

■ Communication systems

■ Cellular phones handsets and accessories

■ Video equipment

Features

■ Ultra low capacitance 1.25 pF max.

■ Bi-directional protection

■ RoHS package

Description

The ESDAULC6-3Bxx is a monolithic application

specific discrete device dedicated to ESD

protection of high speed interfaces such as

USB2.0.

The device is ideal for applications where both

reduced print circuit board space and power

absorption capability are required.

Benefits

■ Ultra low capacitance bidirectional ESD

protection

■ Low PCB space consumption:

2.5 mm

max footprint (1.7 mm

for Flip-Chip)

■ Enhanced ESD protection:

– 15 kV contact discharge

– 15 kV air discharge

■ No insertion loss to 3.0 GHz

■ Ultra low leakage current

■ High reliability offered by monolithic integration

Figure 1. Functional diagram

Figure 2. Pin configuration

Complies with the following standards:

Table 1. Order codes

Part number Marking

ESDAULC6-3BP6 3

ESDAULC6-3BF2 3B

IEC 61000-4-2 level 4:

8 kV (contact discharge)

15 kV (air discharge)

MIL STD 883G-Method 3015-7: class 3B

HBM (Human Body Model)

SOT-666

ESDAULC6-3BP6

Flip-Chip

ESDAULC6-3BF2

I/O1

I/O2

GND

NCNC

I/O3

I/O2 I/O3

I/O1

GND

Top view

ESDAULC6-3BP6

Bump side view

ESDAULC6-3BF2

GND

I/O1 I/O2 I/O3

www.st.com

Summary of content (11 pages)

PAGE 1
ESDAULC6-3BP6 ESDAULC6-3BF2 ESD protection for high speed interface Main applications Where transient overvoltage protection in ESD sensitive equipment is required, such as: ■ Computers ■ Printers ■ Communication systems ■ Cellular phones handsets and accessories ■ Video equipment SOT-666 ESDAULC6-3BP6 Figure 1. Flip-Chip ESDAULC6-3BF2 Functional diagram Features ■ Ultra low capacitance 1.25 pF max.
PAGE 2
Characteristics 1 ESDAULC6-3BP6, ESDAULC6-3BF2 Characteristics Table 2. Absolute maximum ratings Symbol Parameter Peak pulse voltage (1) VPP Value (min.) Unit IEC 61000-4-2 contact discharge IEC 61000-4-2 air discharge 15 15 kV 150 °C -55 to +150 °C 260 °C Maximum operating junction temperature Tj Tstg Storage temperature range Maximum lead temperature for soldering during 10 s at 5 mm for case TL 1. For a surge greater than the maximum values, the diode will fail in short-circuit.
PAGE 3
ESDAULC6-3BP6, ESDAULC6-3BF2 Figure 3. Characteristics Relative variation of peak pulse power versus initial junction temperature (SOT-666) Figure 4. PPP[Tj initial] / PPP[Tj initial=25°C) Relative variation of peak pulse power versus initial junction temperature (Flip-Chip) PPP [T j initial] / PPP [T j initial=25°C] 1.1 1.1 1.0 1.0 0.9 0.9 0.8 0.8 0.7 0.7 0.6 0.6 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 Tj(°C) Tj(°C) 0.0 0.0 0 0 25 Figure 5.
PAGE 4
Characteristics Figure 9. ESDAULC6-3BP6, ESDAULC6-3BF2 Junction capacitance versus reverse voltage applied (typical values) (SOT-666) Figure 10. Junction capacitance versus reverse voltage applied (typical values) (Flip-Chip) C(pF) C(pF) 2 1 F=1MHz VOSC=30mVRMS Tj=25°C F=1MHz VOSC=30mVRMS Tj=25°C 1 VLINE(V) VLINE(V) 0 0 0 1 2 3 4 5 0 1 2 4 5 Figure 12. Relative variation of leakage current versus junction temperature (typical values) (Flip-Chip) Figure 11.
PAGE 5
ESDAULC6-3BP6, ESDAULC6-3BF2 Characteristics 10 V/div Figure 16. Remaining voltage after ESDAULC6-3BF2 during ESD 15 kV negative surge (air discharge) (Flip-Chip) 10 V/div Figure 15. Remaining voltage after ESDAULC6-3BP6 during ESD 15 kV negative surge (air discharge) (SOT-666) 0.1 µs/div 0.1 µs/div Figure 17. S21 attenuation measurement Figure 18. S21 attenuation measurement results of each channel (SOT-666) results of channel 1 (Flip-Chip) 0.00 dB 0.00 - 5.00 - 5.00 - 10.00 - 10.00 - 15.
PAGE 6
Application examples 2 ESDAULC6-3BP6, ESDAULC6-3BF2 Application examples USB 2.0 CONNECTOR Figure 21. USB2.0 (high speed) protection application schematic V BUS D+ IC to Protect DGND Figure 22. Audio jack protection application schematic Audio jack 100pF 330nH FM Tuner MEMORY CONNECTOR Figure 23.
PAGE 7
ESDAULC6-3BP6, ESDAULC6-3BF2 3 Ordering information scheme Ordering information scheme ESDA ULC 6 - 3 B xx ESD Array Ultra low capacitance Breakdown Voltage 6 = 6 Volts Number of lines protected 3 = 3 lines Type B = Bidirectional Packages F2 = Flip-Chip P6 = SOT-666 7/11
PAGE 8
Package information 4 ESDAULC6-3BP6, ESDAULC6-3BF2 Package information ● Epoxy meets UL 94, V0 Table 4. SOT-666 dimensions Dimensions b1 Ref. Millimeters Inches L1 Min. L3 Typ. Max. Min. Typ. Max. A 0.45 0.60 0.018 0.024 A3 0.08 0.18 0.003 0.007 b 0.17 0.34 0.007 0.013 b1 0.19 D 1.50 1.70 0.059 0.067 E 1.50 1.70 0.059 0.067 E1 1.10 1.30 0.043 0.051 b D E1 0.27 0.34 0.007 0.011 0.013 A L2 E A3 e 0.50 0.020 L1 0.19 0.007 L2 0.10 0.30 0.004 0.
PAGE 9
ESDAULC6-3BP6, ESDAULC6-3BF2 Package information Figure 25. Flip-Chip dimensions 650 µm ± 65 1.6 mm ± 50µm 1.0 mm ± 50 µm 500 µm ± 50 315 µm ± 50 1.1 mm ± 50 µm Figure 26. Flip-Chip footprint Figure 27. Flip-Chip marking Dot, ST logo xx = marking z = manufacturing location yww = datecode (y = year ww = week) Copper pad Diameter: 220 µm recommended Solder stencil opening: 330 µmrecommended E x x z y ww Solder mask opening recommendation: 300 µmrecommended Figure 28.
PAGE 10
Ordering information 5 Ordering information Table 5. 6 Ordering information Part number Marking Package Weight Base qty Delivery mode ESDAULC6-3BP6 3 SOT-666 2.9 mg 5000 Tape and reel ESDAULC6-3BF2 3B Flip-Chip 2.22 mg 5000 Tape and reel Revision history Table 6.
PAGE 11
ESDAULC6-3BP6, ESDAULC6-3BF2 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.