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October 2010 Doc ID 11555 Rev 5 1/12

ESDALC6V1M3

Dual low capacitance Transil™ array for ESD protection

Features

■ 2 unidirectional, low capacitance Transil diodes

■ Better than IEC 61000-4-2 standard (ESD

protection: 11 kV contact discharge)

■ Breakdown voltage V

= 6.1 V min

■ Low diode capacitance (11 pF typ at 0 V)

■ Low leakage current < 0.5 µA

■ Very small PCB area: 0.6 mm

■

RoHS compliant

Benefits

■ High ESD protection level

■ High integration

■ Suitable for high density boards

Complies with the following standards

■ IEC61000-4-2 level 4:

– 15 kV (air discharge)

– 8 kV (contact discharge)

■ MIL STD 883G-Method 3015-7: class 3B:

– HBM (human body model)

Applications

Where transient overvoltage protection in ESD

sensitive equipment is required, such as:

■ Computers

■ Printers

■ Communication systems

■ Cellular phone handsets and accessories

■ Video equipment

Figure 1. Functional diagram

Description

The ESDALC6V1M3 is a monolithic array

designed to protect 1 line or 2 lines against ESD

transients.

The device is ideal for applications where both

reduced line capacitance and board space saving

are required.

TM: Transil is a trademark of STMicroelectronics

SOT883

(JEDEC MO-236AA)

GND

I/O2

GND

I/O1

GND

Underside view

www.st.com

Summary of content (12 pages)

PAGE 1
ESDALC6V1M3 Dual low capacitance Transil™ array for ESD protection Features ■ 2 unidirectional, low capacitance Transil diodes ■ Better than IEC 61000-4-2 standard (ESD protection: 11 kV contact discharge) ■ Breakdown voltage VBR = 6.1 V min ■ Low diode capacitance (11 pF typ at 0 V) ■ Low leakage current < 0.5 µA ■ Very small PCB area: 0.6 mm2 ■ RoHS compliant SOT883 (JEDEC MO-236AA) Figure 1.
PAGE 2
Characteristics 1 ESDALC6V1M3 Characteristics Table 1.
PAGE 3
ESDALC6V1M3 Figure 3. Characteristics Relative variation of peak pulse power versus initial junction temperature Figure 4. PPP[Tj initial] /PPP[Tj initial=25°C] 1.1 1000 Peak pulse power versus exponential pulse duration PPP(W) Tj initial = 25 °C 1.0 0.9 0.8 0.7 0.6 100 0.5 0.4 0.3 0.2 0.1 Tj(°C) 0 25 Figure 5. 10.0 tp(µs) 10 0.0 50 75 100 125 1 150 Clamping voltage versus peak pulse current (typical values) 10 Figure 6. IPP(A) 1.
PAGE 4
Characteristics Figure 9. ESDALC6V1M3 ESD response to IEC61000-4-2 (+15 kV air discharge) on each channel Figure 11. S21 attenuation measurement results of each channel Figure 10. ESD response to IEC61000-4-2 (-15 kV air discharge) on each channel Figure 12. Analog crosstalk measurements between channels dB dB 0.00 0.00 - 10.00 - 30.00 - 20.00 - 60.00 - 30.00 - 90.00 F (Hz) F (Hz) - 40.00 100.0k - 120.00 1.0M 10.0M 100.0M 100.0k 1.0G 4/12 1.0M Xtalk Att 1 Doc ID 11555 Rev 5 10.
PAGE 5
ESDALC6V1M3 2 Ordering information Ordering information Figure 13. Ordering information scheme ESDA LC 6V1 M3 ESD array Low capacitance Breakdown voltage 6V1 = 6.1 Volts min.
PAGE 6
Package information 3 ESDALC6V1M3 Package information ● Epoxy meets UL94, V0 ● Lead-free packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 3. SOT883 dimensions Dimensions L1 b1 Ref. L2 2 Min. 3 e b2 1 e1 A Max. Min. Typ. 0.50 0.016 0.
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ESDALC6V1M3 Package information Figure 16. Packing information Cathode bar Ø 1.55 4.0 2.0 1.75 0.20 3.5 1.10 8.0 K K K 0.68 K K All dimensions in mm K K 0.6 2.
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Recommendation on PCB assembly ESDALC6V1M3 4 Recommendation on PCB assembly 4.1 Stencil opening design 1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness). Figure 17. Stencil opening dimensions L T b) W General design rule Stencil thickness (T) = 75 ~ 125 µm W Aspect Ratio = ----- ≥ 1.5 T L×W Aspect Area = ---------------------------- ≥ 0.66 2T ( L + W ) 2.
PAGE 9
ESDALC6V1M3 4.2 4.3 4.4 Recommendation on PCB assembly Solder paste 1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. 2. “No clean” solder paste is recommended. 3. Offers a high tack force to resist component movement during high speed. 4. Solder paste with fine particles: powder particle size is 20-45 µm. Placement 1. Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. 3.
PAGE 10
Recommendation on PCB assembly 4.5 ESDALC6V1M3 Reflow profile Figure 19. ST Ecopack® recommended soldering reflow profile for PCB mounting Temperature (°C) 260°C max 255°C 220°C 180°C 125 °C 2°C/s recommended 2°C/s recommended 6°C/s max 6°C/s max 3°C/s max 3°C/s max 0 0 1 2 3 4 5 10-30 sec 90 to 150 sec Note: 10/12 6 7 Time (min) 90 sec max Minimize air convection currents in the reflow oven to avoid component movement.
PAGE 11
ESDALC6V1M3 5 Ordering information Ordering information Table 4. Ordering information Order code Marking Package Weight Base qty Delivery mode ESDALC6V1M3 K(1) SOT883 0.86 mg 12000 Tape and reel 1. The marking can be rotated by 90° to differentiate assembly location 6 Revision history Table 5. Document revision history Date Revision Changes 04-Aug-2005 1 Initial release. 23-May-2006 2 Reformated to current standards. Added soldering reflow profile diagram.
PAGE 12
ESDALC6V1M3 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.