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March 2011 Doc ID 16741 Rev 2 1/11

ESDALC6V1-5T6

Low capacitance Transil™ arrays for ESD protection

Features

■ 5 unidirectional Transil diodes

■ Breakdown voltage V

= 6.1 V min.

■ Low diode capacitance: 7 pF typ.

■ Low leakage current < 100 nA

■ Very small PCB area: 1.0 mm²

■ 350 µm pitch micro-package

■ Lead-free and RoHS package

Complies with the following standards

■ IEC 61000-4-2:

– 15 kV (air discharge)

– 8 kV (contact discharge)

■ MIL STD 883G- Method 3015-7: class3B:

– >8 kV (human body model)

Applications

Where transient overvoltage protection in ESD

sensitive equipment is required, such as:

■ Cellular phone handsets and accessories

■ Computers

■ Printers

■ Communication systems

■ Video equipment

■ Set top boxes

Description

The ESDALC6V1-5T6 is monolithic arrays

designed to protect up to 5 lines against ESD

transients.

The device is ideal for applications where both

reduced print circuit board space and high ESD

protection level are required.

Figure 1. Functional diagram (top view)

TM: Transil is a trademark of STMicroelectronics

Micro DFN package

1.0 x 1.0-6L

www.st.com

Summary of content (11 pages)

PAGE 1
ESDALC6V1-5T6 Low capacitance Transil™ arrays for ESD protection Features ■ 5 unidirectional Transil diodes ■ Breakdown voltage VBR = 6.1 V min. ■ Low diode capacitance: 7 pF typ. ■ Low leakage current < 100 nA ■ Very small PCB area: 1.0 mm² ■ 350 µm pitch micro-package ■ Lead-free and RoHS package Micro DFN package 1.0 x 1.
PAGE 2
Characteristics 1 ESDALC6V1-5T6 Characteristics Table 1. Absolute maximum ratings (Tamb = 25 °C) Symbol Parameter VPP ESD IEC 61000-4-2, air discharge ESD IEC 61000-4-2, contact discharge PPP Peak pulse power dissipation (8/20 µs)(1) Ipp Repetitive peak pulse current typical value (8/20 µs) Tj Junction temperature Tstg Unit 15 8 kV 25 W 2 A 125 °C -55 + 150 °C 260 °C Tj initial = Tamb Storage temperature range TL Value Maximum lead temperature for soldering during 10 s 1.
PAGE 3
ESDALC6V1-5T6 Figure 3. Characteristics Relative variation of peak pulse power versus initial junction temperature Figure 4. PPP[Tjinitial]/PPP[Tjinitial = 25 °C] 1.1 Peak pulse power versus exponential pulse duration PPP(W) 1000 Tjinitial = 25 °C 1.0 0.9 0.8 100 0.7 0.6 0.5 0.4 10 0.3 0.2 0.1 Tj(°C) 0.0 0 25 Figure 5. 10.0 50 75 100 125 1 150 Clamping voltage versus peak pulse current (typical values, exponential waveform) tp (µs) 1 10 Figure 6.
PAGE 4
Ordering information scheme Figure 9. 0.00 ESDALC6V1-5T6 S21 attenuation measurement results of each channel Figure 10. Analog crosstalk measurements between channels dB 0.00 dB -20.00 -5.00 -40.00 -10.00 -60.00 -15.00 -80.00 -20.00 -100.00 -25.00 -120.00 F/Hz -30.00 100.0K 1.0M 10.0M 100.0M Figure 11. ESD response to IEC 61000-4-2 (+15 kV air discharge) on each channel F/Hz -140.00 100.0K 1.0G 1.0M 10.0M 100.0M 1.0G Figure 12.
PAGE 5
ESDALC6V1-5T6 3 Package information Package information ● Epoxy meets UL94, V0 ● Lead-free package In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 3. Micro DFN 1.0 x 1.0-6L dimensions Dimensions Ref. Typ. Max. Min. Typ. Max. A 0.31 - 0.40 0.
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Package information ESDALC6V1-5T6 Figure 16. Tape and reel specifications 2.0 ± 0.05 4.0 ± 0.1 Ø 1.50 + 0.10 / -0.00 1.75 ± 0.1 Dot identifying Pin 1 location 3.5 ± 0.05 1.13 ± 0.05 8.0 ± 0.3 0.23 ± 0.02 K K 1.13 ± 0.05 K 2.0 ± 0.05 0.53± 0.
PAGE 7
ESDALC6V1-5T6 Recommendation on PCB assembly 4 Recommendation on PCB assembly 4.1 Stencil opening design 1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness). Figure 17. Stencil opening dimensions L T b) W General design rule Stencil thickness (T) = 75 ~ 125 µm W Aspect Ratio = ----- ≥ 1.5 T L×W Aspect Area = ---------------------------- ≥ 0.66 2T ( L + W ) 2.
PAGE 8
Recommendation on PCB assembly 4.2 4.3 4.4 8/11 ESDALC6V1-5T6 Solder paste 1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. 2. “No clean” solder paste is recommended. 3. Offers a high tack force to resist component movement during high speed. 4. Solder paste with fine particles: powder particle size is 20-45 µm. Placement 1. Manual positioning is not recommended. 2.
PAGE 9
ESDALC6V1-5T6 4.5 Recommendation on PCB assembly Reflow profile Figure 19. ST ECOPACK® recommended soldering reflow profile for PCB mounting Temperature (°C) 260°C max 255°C 220°C 180°C 125 °C 2°C/s recommended 2°C/s recommended 6°C/s max 6°C/s max 3°C/s max 3°C/s max 0 0 1 2 3 4 5 10-30 sec 90 to 150 sec Note: 6 7 Time (min) 90 sec max Minimize air convection currents in the reflow oven to avoid component movement.
PAGE 10
Ordering information 5 ESDALC6V1-5T6 Ordering information Table 4. Ordering information Order code Marking Package Weight Base qty Delivery mode ESDALC6V1-5T6 K(1) DFN1.0 x1.0-6L 1.78 mg 3000 Tape and reel 1. The marking can be rotated by multiples of 90° to differentiate assembly location 6 Revision history Table 5. 10/11 Document revision history Date Revision Changes 05-Nov-2009 1 Initial release. 03-Mar-2011 2 Added Figure 15 and following note. Added footnote toTable 4.
PAGE 11
ESDALC6V1-5T6 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.