Datasheet

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This is information on a product in full production.

June 2012 Doc ID 15025 Rev 3 1/11

ESDALC12-1T2

Single line transient surge voltage suppressor (TVS)

for data and power line

Datasheet − production data

Features

■ Stand-off voltage 10 V

■ Unidirectional device

■ Low clamping factor V

■

Breakdown voltage V

= 12 V min.

■ Fast response time

■ Very thin package: 0.4 mm

■ Low leakage current

■ RoHS compliant

Benefits

■ High ESD robustness of the application

■ Suitable for high density boards

Complies with the following standards:

■ IEC 61000-4-2 level 4:

– 15 kV (air discharge)

– 8 kV (contact discharge)

■ MIL STD 883G - Method 3015-7: class 3B

Applications

Where transient overvoltage protection and

electrical overstress protection in sensitive

equipment are required, such as:

■ Computers

■ Printers

■ Communication systems

■ Cellular phone handsets and accessories

■ Video equipment

Figure 1. Functional diagram

Description

The ESDALC12-1T2 is a unidirectional single line

Transil™ diode designed specially for protection

of integrated circuits in portable equipment and

miniaturized electronic devices subjected to ESD

and EOS transient over voltages. Packed in

SOD882T, it minimizes PCB occupation.

TM: Transil is a trademark of STMicroelectronics

SOD882T

GND

I/O1

GND

www.st.com

Summary of content (11 pages)

PAGE 1
ESDALC12-1T2 Single line transient surge voltage suppressor (TVS) for data and power line Datasheet − production data Features ■ Stand-off voltage 10 V ■ Unidirectional device ■ Low clamping factor VCL/VBR ■ Breakdown voltage VBR = 12 V min. ■ Fast response time ■ Very thin package: 0.4 mm ■ Low leakage current ■ RoHS compliant SOD882T Benefits ■ High ESD robustness of the application ■ Suitable for high density boards Figure 1.
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Characteristics ESDALC12-1T2 1 Characteristics Table 1. Absolute maximum ratings (Tamb = 25 °C) Symbol Parameter VPP Peak pulse voltage - IEC 61000-4-2 Air discharge Contact discharge PPP Peak pulse power dissipation (8/20 µs) (1) Value Unit 25 20 kV 50 W 2 A Tj initial = Tamb (1) IPP Peak pulse current (8/20 µs) Tj Operating junction temperature range - 40 to + 125 °C Storage temperature range - 55 to +150 °C Tstg 1.
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ESDALC12-1T2 Figure 3. 100 Characteristics Peak pulse power dissipation versus initial junction temperature PPP(W) Figure 4. Peak pulse power versus exponential pulse duration PPP(W) 1000 8/20 µs Tj initial = 25 °C 90 Tj = 125 °C 80 70 100 60 50 40 10 30 20 10 Tj(°C) 0 0 25 Figure 5. 10.0 50 75 100 125 150 TP(µs) 1 175 Clamping voltage versus peak pulse current (maximum values) 1 10 Figure 6. IPP(A) 10.
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Characteristics Figure 9. ESDALC12-1T2 ESD response to IEC 61000-4-2 (+15 kV air discharge) on each channel Figure 10. ESD response to IEC 61000-4-2 (-15 kV air discharge) on each channel 5 V/div 10 V/div 100 ns/div 100 ns/div Figure 11. S21 attenuation measurement 0.00 dB -5.00 -10.00 -15.00 -20.00 -25.00 F (Hz) -30.00 300.0k 4/11 1.0M 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G Doc ID 15025 Rev 3 3.
PAGE 5
ESDALC12-1T2 2 Ordering information scheme Ordering information scheme Figure 12. Ordering information scheme ESDA LC 12 - 1 T2 ESD array Low capacitance Breakdown voltage 12 = 12 Volt min.
PAGE 6
Package information 3 ESDALC12-1T2 Package information ● Epoxy meets UL94, V0 ● Lead-free package In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 13. SOD882 dimension definitions L1 L2 b1 b2 PIN # 1 ID e A A1 E D Table 3.
PAGE 7
ESDALC12-1T2 Package information Figure 14. Footprint (dimensions in mm) Figure 15. Marking 0.55 (0.022) 0.55 (0.022) 0.50 0.020 Pin1 0.40 (0.016) Note: I VN Pin2 2 Pin Product marking may be rotated by multiples of 90° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. Figure 16. Tape and reel specifications Cathode bar Ø 1.55 2.0 4.0 1.75 0.20 3.5 1.10 8.
PAGE 8
Recommendation on PCB assembly ESDALC12-1T2 4 Recommendation on PCB assembly 4.1 Stencil opening design 1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness). Figure 17. Stencil opening dimensions L T b) W General design rule Stencil thickness (T) = 75 ~ 125 µm W Aspect Ratio = ----- ≥ 1.5 T L×W Aspect Area = ---------------------------- ≥ 0.66 2T ( L + W ) 2.
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ESDALC12-1T2 4.3 4.4 4.5 Recommendation on PCB assembly Placement 1. Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering 3. Standard tolerance of ± 0.05 mm is recommended. 4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short.
PAGE 10
Ordering information 5 ESDALC12-1T2 Ordering information Table 4. Ordering information Order code Marking Package Weight Base qty Delivery mode ESDALC12-1T2 V(1) SOD882T 0.76 mg 12000 Tape and reel 1. The marking can be rotated by multiples of 90° to differentiate assembly location 6 Revision history Table 5. 10/11 Document revision history Date Revision Changes 16-Sep-2008 1 Initial release 02-Nov-2010 2 Updated Table 1, base quantity change onTable 4 and updated graphics.
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ESDALC12-1T2 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.