Datasheet

Electrical specifications L9823
10/19 DocID7791 Rev 7
C
OUT
Output capacitance V
OUT
= 16 V; f = 1 MHz - - 300 pF
Outputs short circuit protection
I
SCB
Overcurrent shutoff threshold SFPD = Low, V
OUT
 V
DG
0.5 1.6 2.5 A
I
OUT LIM
Short circuit current limitation - 0.5 1.6 2.5 A
t
dly SCB
Short circuit shutdown delay
SFPD = Low, V
OUT
 V
DG
CSB = 50% to
I
OUT
 1/2 I
OUT LIM
70 150 250 µs
Diagnostics
V
DG
Diagnostic threshold voltage - 0.5 · V
DD
0.55 · V
DD
0.6 · V
DD
V
I
OUT OL
Open load detection sink
current
V
out
= V
DG
Output programmed OFF
30 60 100 µA
t
dly SFPD
Diagnostic detection filter time
SFPD = Low, V
OUT
 V
DG
CSB = 50% to valid data at SO
70 150 250 µs
Outputs timing
t
don
Turn-on delay
CSB = 50% to R
L
= 50 
V
OUT
= 0.9 V
bat
, V
bat
= 16 V
- - 20 µs
t
doff
Turn-off delay
CSB = 50% to R
L
= 50 
V
OUT
= 0.1 · V
bat
, V
bat
= 16 V
- - 20 µs
dV
on/dt
Turn-on voltage slew-rate
90% to 30% of V
bat
;
R
L
= 50 ; V
bat
= 16 V
0.7 2.1 3.5 V/µs
dV
off/dt
Turn-off voltage slew-rate
30% to 90% of V
bat
;
R
L
= 50 ; V
bat
= 16 V
0.7 2.1 3.5 V/µs
dV
off
clamp/dt
Turn-off voltage clamp slew-
rate
30% to 80% of V
OUT clamp
R
L
= 500 
0.7 2.1 5.5 V/µs
Serial diagnostic link (Load capacitor at SO = 200 pF)
f
sclk
Clock frequency 50% duty cycle 3 - - MHz
t
clh
Minimum time SCLK = HIGH - 160 - - ns
t
cll
Minimum time SCLK = LOW - 160 - - ns
t
pcld
Propagation delay
SCLK to data at SO valid
4.9 V  V
DD
 5.1 V - - 100 ns
t
csdv
CSB = LOW to data at SO
active
- - - 100 ns
t
sclch
SCLK low before CSB low
Setup time SCLK to CSB change
H/L
100 - - ns
t
hclcl
SCLK change L/H after CSB =
Low
Setup time CSB to SCLK change
L/H
100 - - ns
t
scld
SI input setup time
SCLK change H/L after SI data
valid
20 - - ns
Table 5. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit