Datasheet

L6219 Block diagram
7/16
Note: ESD on GND, V
S
, V
SS
, OUT 1 A and OUT 2 A is guaranteed up to 1.5 KV (human body
model, 1500 W, 100 pF).
Figure 3. Timing diagram
10, 16 Phase
This TTL-compatible logic inputs sets the direction of
current flow through the load. A high level causes current to
flow from output A (source) to output B (sink). A schmitt
trigger on this input provides good noise immunity and a
delay circuit prevents output stage short circuits during
switching
11, 15 Reference voltage
A voltage applied to this pin sets the reference voltage of the
comparators, this determining the output current (also thus
depending on Rs and the two inputs input 0 and input 1)
12, 14 RC
A parallel RC network connected to this pin sets the OFF
time of the higher power transistors. The pulse generator is
a monostable triggered by the output of the comparators
(toff = 1.1 RT CT)
13 V
SS
- Logic supply Supply voltage input for logic circuitry
24 V
S
- Load supply Supply voltage input for the output stages
Table 3. Pin functions (continued)
Pin # Name Description
Table 4. Thermal data
Parameter Description PDIP SO Unit
R
thj-case
Thermal resistance junction-case max. 14 18 °C/W
R
thj-amb
Thermal resistance junction-ambient max. 60
(1)
1. With minimized copper area.
75
(1)
°C/W