User Manual

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Document ID: PB-ZB-MOD-003-20DS
Table 5.1: Pad Description (cont)
Pad#
Signal
Direction
Description
24
PC3
I/O
Digital I/O Either Enable with GPIO_DBGCFG[5], or enable Serial Wire mode
(see JTMS description, Pad 26)
JTDI
1
JTAG data in from debugger Selected when in JTAG mode (default
mode, see JTMS description, Pad 26).
Internal pull-up is enabled.
25
GND
Power
Ground supply pad.
26
PC4
I/O
Digital I/O Enable with GPIO_DBGCFG[5]
JTMS
I
JTAG mode select from debugger.
Selected when in JTAG mode (default mode).
JTAG mode is enabled after power-up or by forcing nRESET low.
Select Serial Wire mode using the ARM-defined protocol through a debugger.
Internal pull-up is enabled.
SWDIO
I/O
Serial Wire bidirectional data to/from debugger.
Enable Serial Wire mode (see JTMS description).
Select Serial Wire mode using the ARM-defined protocol through a
debugger.
Internal pull-up is enabled.
27
PB0
I/O
Digital I/O
VREF
Analog O
ADC reference output.
Enable analog function with GPIO_PBCFGL[3:0]
VREF
Analog I
ADC reference input.
Enable analog function with GPIO_PBCFGL[3:0].
Enable reference output with an STM system function
IRQA
I
External interrupt source A.
TRACECLK (see
also Pad 16)
O
Synchronous CPU trace clock.
Enable trace interface in ARM core.
Select alternate output function with GPIO_PBCFGL[3:0].
TIM1CLK
I
Timer 1 external clock input
TIM2MSK
I
Timer 2 external clock mask input
28
GND
Power
Ground supply pad.
29
PC1
I/O
Digital I/O
ADC3
Analog
ADC Inputs Enable analog function with GPIO_PCCFGL[7:4]
SWO (see also
Pad 23)
O
Serial Wire Output asynchronous trace output to debugger.
Select asynchronous trace interface in ARM core.
Enable trace interface in ARM core.
Select alternate output function with GPIO_PCCFGL[7:4].
TRACEDATA0
O
Synchronous CPU trace data bit 0.
Select 1-, 2- or 4-wire synchronous trace interface in ARM core.
Enable trace interface in ARM core.
Select alternate output function with GPIO_PCCFGL[7:4].
30
PC0
I/O High current
Digital I/O.
Either enable with GPIO_DBGCFG[5], or enable Serial Wire mode (see
JTMS description, Pad 26) and disable TRACEDATA1.
JRST
I
JTAG reset input from debugger.
Selected when in JTAG mode (default mode, see JTMS description) and
TRACEDATA1 is disabled.
Internal pull-up is enabled.
IRQD1
I
Default external interrupt source D
TRACEDATA1
O
Synchronous CPU trace data bit 1.
Select 2- or 4-wire synchronous trace interface in ARM core.
Enable trace interface in ARM core.
Select alternate output function with GPIO_PCCFGL[3:0].