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May 2008 Rev 1 1/17

DVIULC6-2x6

Ultra low capacitance ESD protection

Features

■ 2-line ESD protection (at 15 kV air and contact

discharge, exceeds IEC 61000-4-2)

■ Protects V

BUS

when applicable

■ Ultra low capacitance: 0.6 pF at F = 825 MHz

■ Fast response time compared with varistors

■ Low leakage current: 0.5 µA max

■ RoHS compliant

Benefits

■ ESD standards compliance guaranteed at

device level, hence greater immunity at system

level

■ ESD protection of V

BUS

when applicable.

■ Large bandwidth to minimize impact on data

signal quality

■ Consistent D+ / D- signal balance:

– Ultra low impact on intra- and inter-pair

skew

– Matching high bit rate DVI, and IEEE 1394

requirements

■ Low PCB space consumption - 1.45 mm

for µQFN

■ Low leakage current for longer operation of

battery powered devices

■ Higher reliability offered by monolithic

integration

■ 500 µm pitch for µQFN 6 leads

Complies with these standards

■ IEC 61000-4-2 level 4

– 15 kV air discharge

– 8 kV contact discharge

■ MIL STD883G-Method 3015-7

Applications

■ DVI ports up to 1.65 Gb/s

■ IEEE 1394a, b, and c up to 3.2 Gb/s

■ USB2.0 ports up to 480 Mb/s (high speed),

backwards compatible with USB1.1 low and full

speed

■ Ethernet port: 10/100/1000 Mb/s

■ SIM card protection

■ Video line protection

Description

The DVIULC6-2x6 is a monolithic, application

specific discrete device dedicated to ESD

protection of high speed interfaces, such as DVI,

IEEE 1394a, b and c, USB2.0, Ethernet links and

video lines.

Its ultra low line capacitance secures a high level

of signal integrity without compromising in

protecting sensitive chips against the most

stringently characterized ESD strikes.

µQFN (pin view)

DVIULC6-2M6

SOT-666

DVIULC6-2P6

www.st.com

Summary of content (17 pages)

PAGE 1
DVIULC6-2x6 Ultra low capacitance ESD protection Features ■ 2-line ESD protection (at 15 kV air and contact discharge, exceeds IEC 61000-4-2) ■ Protects VBUS when applicable ■ Ultra low capacitance: 0.6 pF at F = 825 MHz ■ Fast response time compared with varistors ■ Low leakage current: 0.
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Characteristics 1 DVIULC6-2x6 Characteristics Figure 1. Functional diagram I/O1 1 6 I/O1 VBUS GND 2 5 VBUS I/O2 I/O2 3 4 I/O2 I/O1 1 6 I/O1 GND 2 5 I/O2 3 4 µQFN 6 leads SOT666 When used with a DVI application, Pin 5 should not be connected to protect against backdrive current flow on data lines. Table 1.
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DVIULC6-2x6 Figure 2. Characteristics Line capacitance versus line voltage (typical values) Figure 3. C(pF) Line capacitance versus frequency (typical values) DVIULC6-2M6 C(pF) 1.0 1.0 F=825MHz Vosc=500mVRMS VBUS OPEN Tj =25 °C 0.9 0.8 0.7 Vosc=30mVRMS Tj =25°C VI-O/GND = 0V VBUS OPEN 0.9 0.8 0.7 0.6 0.6 0.5 CI/O - GND 0.5 0.4 0.4 0.3 0.3 0.2 CI/O - GND 0.2 0.1 CI/O - CI/O 0.1 Data line voltage (v) 0 F(MHz) 0 0.0 Figure 4. 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.
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Characteristics Figure 8. Eye diagram at 1.65 Gbps amplitude 500 mV PCB + DVIULC6-2M6 Horizontal: 100 ps/div Vertical: 200 mV/div Figure 10. Eye diagram at 1.65 Gbps amplitude 500 mV PCB + DVIULC6-2P6 Horizontal: 100 ps/div Vertical: 200 mV/div 4/17 DVIULC6-2x6 Figure 9. Eye diagram at 3.2 Gbps amplitude 500 mV PCB + DVIULC6-2M6 Horizontal: 50 ps/div Vertical: 200 mV/div Figure 11. Eye diagram at 3.
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DVIULC6-2x6 2 Application examples Application examples Figure 12.
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Application examples 2.1 DVIULC6-2x6 PCB layout considerations Figure 14. PCB layout example Width=100 µm Space=400 µm All dimensions in µm 3160 3160 Width=215 µm PCB Characteristics Space=100 µm Substrate: H = 730 m, Er =3.9 Z0diff=100 Ω Tracks: H = 35 µm copper Coatinbg: H = 35 µm above substrate: H = 10 µm above tracks, Er = 3.4 GND plane on the bottom layer Figure 15.
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DVIULC6-2x6 Technical information 3 Technical information 3.1 Surge protection The DVIULC6-2x6 is particularly optimized to perform ESD surge protection based on the rail to rail topology. The clamping voltage VCL can be calculated as follows: VCL+ = VTRANSIL + VF for positive surges VCL- = - VF for negative surges with: VF = VT + Rd.Ip (VF forward drop voltage) / (VT forward drop threshold voltage) and VTRANSIL = VBR + Rd_TRANSIL .
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Technical information DVIULC6-2x6 Figure 16. IESD behavior: parasitic phenomena due to unsuitable layout ESD surge on data line VCL+ VBUS Data line LI/O LI/O di L VBUS dt L I/O di di + L GND dt dt POSITIVE SURGE Vcc pin VF VTRANSIL VTRANSIL +VF VCL I/O pin t tr=1ns GND pin LGND LGND tr=1ns di dt t -VF di di + L GND dt dt di di - L GND dt dt VCL + = VTRANSIL + VF + L I/O surge > 0 VCL - = - VF - L I/O surge < 0 - L I/O di di - L GND dt dt NEGATIVE SURGE VTRANSIL = VBR + Rd.
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DVIULC6-2x6 Technical information Figure 20. Remaining voltage after the DVIULC6-2P6 during positive ESD surge Figure 21. Remaining voltage after the DVIULC6-26 during negative ESD surge 10V/Div 10V/Div 100ns/Div 100ns/Div Important An important precaution to take is to put the protection device as close as possible to the disturbance source (generally the connector). 3.3 Crosstalk behavior Figure 22.
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Technical information DVIULC6-2x6 Figure 23. Analog crosstalk measurements TEST BOARD NETWORK ANALYSER PORT 2 NETWORK ANALYSER PORT 1 Figure 23 gives the measurement circuit for the analog application. In usual frequency range of analog signals (up to 240 MHz) the effect on disturbed line is less than -40 dB (see Figure 24, and Figure 25). Figure 24. Analog crosstalk results (typical values) for DVIULC6-2M6 dB 0.00 -7.6dB@7GHz - 30.00 - 60.00 - 90.00 F (Hz) - 120.00 300.0k 1.0M 3.0M 10.0M 30.
PAGE 11
DVIULC6-2x6 Recommendation on PCB assembly 4 Recommendation on PCB assembly 4.1 Stencil opening design 1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness) Figure 26. Stencil opening dimensions. L T b) W General Design Rule Stencil thickness (T) = 75 ~ 125 µm W Aspect Ratio = ----- ≥ 1.5 T L×W Aspect Area = ---------------------------- ≥ 0.66 2T ( L + W ) 2.
PAGE 12
Recommendation on PCB assembly 4.2 4.3 4.4 12/17 DVIULC6-2x6 Solder paste 1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. 2. “No clean” solder paste is recommended. 3. Offers a high tack force to resist component movement during high speed. 4. Solder paste with fine particles: powder particle size is 20-45 µm. Placement 1. Manual positioning is not recommended. 2.
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DVIULC6-2x6 4.5 Recommendation on PCB assembly Reflow profile Figure 28. ST ECOPACK® recommended soldering reflow profile for PCB mounting Temperature (°C) 260°C max 255°C 220°C 180°C 125 °C 2°C/s recommended 2°C/s recommended 6°C/s max 6°C/s max 3°C/s max 3°C/s max 0 0 1 2 3 4 5 10-30 sec 90 to 150 sec Note: 6 7 Time (min) 90 sec max Minimize air convection currents in the reflow oven to avoid component movement.
PAGE 14
Package information 5 DVIULC6-2x6 Package information ● Epoxy meets UL94, V0 In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark.
PAGE 15
DVIULC6-2x6 Package information Table 4. SOT-666 dimensions Dimensions b1 Ref. Millimeters Inches L1 Min. L3 Typ. Max. Min. Typ. Max. A 0.45 0.60 0.018 0.024 A3 0.08 0.18 0.003 0.007 b 0.17 0.34 0.007 0.013 b1 0.19 D 1.50 1.70 0.059 0.067 E 1.50 1.70 0.059 0.067 E1 1.10 1.30 0.043 0.051 b D E1 0.27 0.34 0.007 0.011 0.013 A L2 E A3 e 0.50 0.020 L1 0.19 0.007 L2 0.10 0.30 0.004 0.012 e L3 0.10 0.004 Figure 30. Footprint (dimensions in mm) 0.50 0.
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Ordering information 6 DVIULC6-2x6 Ordering information Table 5. Ordering information Order code Marking Package Weight Base qty Delivery mode DVIULC6-2M6 T(1) µQFN 6 leads 2.2 mg 3000 Tape and reel DVIULC6-2P6 R SOT-666 2.9 mg 3000 Tape and reel 1. The marking can be rotated by 90° to diferentiate assembly location 7 Revision history Table 6. 16/17 Document revision history Date Revision 06-May-2008 1 Description of changes First issue.
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DVIULC6-2x6 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.