Datasheet

DALC208 Technical information
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Figure 8. ESD behavior: parasitic phenomena due to unsuitable layout
2.3 How to ensure good ESD protection
While the DALC208SC6 provides a high immunity to ESD surge, an efficient protection
depends on the layout of the board. In the same way, with the rail to rail topology, the track
from the V
REF2
pin to the power supply +V
CC
and from the V
REF1
pin to GND must be as short
as possible to avoid over voltages due to parasitic phenomena. See Figure 8.
It’s often harder to connect the power supply near to the DALC208SC6 unlike the ground
thanks to the ground plane that allows a short connection.
To ensure the same efficiency for positive surges when the connections can’t be short
enough, we recommend putting a capacitance of 100 nF close to the DALC208SC6,
between V
REF2
and ground, to prevent these kinds of overvoltage disturbances.
See Figure 9.
The addition of this capacitance will allow a better protection by providing a constant voltage
during a surge.
Figure 10, Figure 11, and Figure 12 show the improvement of the ESD protection according
to the recommendations described above.
Lw
VI/O
ESD
SURGE
REF1=GND
I/O
REF2=+Vcc
Vf
Lw
di
dt
Lw
di
dt
Vcl+ =
Vcc+Vf+
Lw
di
dt
surge >0
-Vf-
Lw
di
dt
surge <0
Vcl- =
t
tr=1ns
Vcc+Vf
Lw
di
dt
Vcl+
POSITIVE
SURGE
167V
-Lw
di
dt
t
tr=1ns
-Vf
Vcl-
NEGATIVE
SURGE
-162V