Datasheet

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March 2008 Rev 7 1/14

DALC208

Low capacitance diode array

Features

■ Protection of 4 lines

■ Peak reverse voltage: V

RRM

= 9 V per diode

■ Very low capacitance per diode: C < 5 pF

■ Very low leakage current: I

< 1 µA

Benefits

■ Cost-effective solution compared with discrete

solution

■ High efficiency in ESD suppression

■ No significant signal distortion thanks to very

low capacitance

■ High reliability offered by monolithic integration

■ Lower PCB area consumption versus discrete

solution

Complies with the following standards

■ IEC61000-4-2 level 4

■ MIL STD 883G-Method 3015-7: class 3,

human body model

Applications

Where ESD and/or over and undershoot

protection for datalines is required:

■ Sensitive logic input protection

■ Microprocessor based equipment

■ Audio / video inputs

■ Portable electronics

■ Networks

■ ISDN equipment

■ USB interface

Figure 1. Functional diagram

Description

The DALC208SC6 diode array is designed to

protect components which are connected to data

and transmission lines from over voltages caused

by electrostatic discharge (ESD) or other

transients. It is a rail-to-rail protection device also

suited for overshoot and undershoot suppression

on sensitive logic inputs.

The low capacitance of the DALC208SC6

prevents significant signal distortion.

SOT23-6L

(Plastic)

I/O 1

I/O 2 I/O 3

I/O 4

REF 2 REF 1

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Summary of content (14 pages)

PAGE 1
DALC208 Low capacitance diode array Features ■ Protection of 4 lines ■ Peak reverse voltage: VRRM = 9 V per diode ■ Very low capacitance per diode: C < 5 pF ■ Very low leakage current: IR < 1 µA 1 SOT23-6L (Plastic) Benefits ■ Cost-effective solution compared with discrete solution ■ High efficiency in ESD suppression ■ No significant signal distortion thanks to very low capacitance ■ High reliability offered by monolithic integration ■ Lower PCB area consumption versus discrete solution
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Characteristics DALC208 1 Characteristics Table 1. Absolute maximum ratings (Tamb = 25 °C) Value Unit IEC61000-4-2, air discharge IEC61000-4-2, contact discharge 15 8 kV VRRM Peak reverse voltage per diode 9 V ΔVREF Reference voltage gap between VREF2 and VREF1 9 V Symbol VPP Parameter VIn max. Maximum operating signal input voltage VREF2 V VIn min.
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DALC208 Characteristics Figure 3. Maximum non-repetitive peak Figure 4. forward current versus rectangular pulse duration (Tj initial = 25 °C) Reverse clamping voltage versus peak pulse current (Tj initial = 25 °C), typical values. Rectangular waveform tp = 2.5 ms Ipp(A) IFSM(A) 2.0 8 I/O vs REF1 or REF2 7 tp=2.5µs 1.0 6 5 4 3 2 1 tp(ms) 0 0.001 0.01 Figure 5. 0.1 I/O vs REF1 or REF2 VCL(V) 1 10 100 1000 0.1 5 Variation of leakage current versus Figure 6.
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Technical information 2 Technical information 2.1 Surge protection DALC208 The DALC208SC6 is particularly optimized to perform surge protection based on the rail to rail topology. The clamping voltage VCL can be calculated as follow : VCL+ = VREF2 + VF for positive surges VCL- = VREF1 - VF for negative surges with VF = VT + Rd.
PAGE 5
DALC208 Technical information Figure 8. ESD behavior: parasitic phenomena due to unsuitable layout Vcl+ 167V Lw ESD SURGE REF2=+Vcc Vf Lw di dt Lw di dt POSITIVE SURGE Vcc+Vf t I/O tr=1ns VI/O Lw di dt di Vcl+ = Vcc+Vf+Lw dt surge >0 di surge <0 Vcl- = -Vf- Lw dt tr=1ns t -Vf -Lw NEGATIVE SURGE di dt REF1=GND -162V Vcl- 2.3 How to ensure good ESD protection While the DALC208SC6 provides a high immunity to ESD surge, an efficient protection depends on the layout of the board.
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Technical information Figure 9. DALC208 ESD behavior: optimized layout and Figure 10. ESD behavior: measurement add of a capacitance of 100 nF conditions (with coupling capacitance) ESD SURGE Vcl+ TEST BOARD Lw ESD SURGE REF2=+Vcc POSITIVE SURGE C=100nF t DALC 208 I/O VI/O Vcl+ = Vcc+Vf surge >0 Vcl- = surge <0 -Vf t +5V NEGATIVE SURGE REF1=GND Vcl- Figure 11. Remaining voltage after the DALC208SC6 during positive ESD surge Figure 12.
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DALC208 Crosstalk behavior 3 Crosstalk behavior 3.1 Crosstalk phenomena Figure 13. Crosstalk phenomena RG1 Line 1 VG1 RL1 RG2 α 1 VG1 + β12VG2 Line 2 VG2 RL2 DRIVERS α 2VG2 + β21VG1 RECEIVERS The crosstalk phenomenon is due to the coupling between 2 lines. The coupling factor (β12 or β21) increases when the gap across lines decreases, particularly in silicon dice.
PAGE 8
Crosstalk behavior DALC208 Note: The measurements have been done in the worst case i.e. on two adjacent cells (I/O1 and I/O4). 3.3 Analog crosstalk Figure 16. Analog crosstalk measurements TRACKING GENERATOR SPECTRUM ANALYSER TEST BOARD 50Ω DALC 208 +5V 50Ω Vg Vin Vout C=100nF Figure 16 shows the measurement circuit for the analog application. For the usual frequency range of analog signals (up to 100MHz) the effect on disturbed line is less than -45 dBm. See Figure 17. Figure 17.
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DALC208 4 Application examples Application examples Figure 19. Video line protection +Vcc 100nF Pin N° Signal 1 2 RED VIDEO GREEN VIDEO or COMPOSITE SYNC with GREEN VIDEO BLUE VIDEO GROUND DDC (Display Data Channel) GROUND RED GROUND GREEN GROUND BLUE GROUND NC SYNC GROUND GROUND SDA (Sérial Data) HORIZONTAL SYNC or COMPOSITE SYNC VERTICAL SYNC (VCLK) SCL (Serial Clock) DALC 208 5 3 4 5 6 7 8 9 10 11 12 13 1 15 +Vcc DALC 208 100nF 14 15 Figure 20. T1/E1 protection Figure 21.
PAGE 10
PSpice model 5 DALC208 PSpice model Figure 23 shows the PSpice model of one DALC208SC6 cell. In this model, the diodes are defined by the PSpice parameters given in Table 4. Figure 23. PSpice model of one DALC208SC6 Figure 24. PSpice model simulation: surge > 0 cell IEC 61000-4-2 contact discharge response Vref2 Current (A) / Voltage (V) 60 Current Surge 0.8nH 50 0.3Ω I/O Voltage 40 Dpos 0.8nH 0.3Ω 30 I/O Dneg 20 0.5Ω 10 1.
PAGE 11
DALC208 PSpice model Table 4. PSpice parameter Parameter DPOS DNEG BV 9 9 CJO 7p 7p IBV 1u 1u IKF 28.357E-3 1000 IS 118.78E-15 5.6524E-9 ISR 100E-12 472.3E-9 M 0.3333 0.3333 N 1.3334 2.413 NR 2 2 RS 0.68377 0.71677 VJ 0.6 0.
PAGE 12
Package information 6 DALC208 Package information ● Epoxy meets UL94, V0 In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.
PAGE 13
DALC208 7 Ordering information Ordering information Table 6. 8 Ordering information Order code Marking Package Weight Base qty Packing mode DALC208SC6 DALC SOT23-6L 16.7 mg 3000 Tape and reel Revision history Table 7. Document revision history Date Revision Changes Feb-2002 5C 28-Oct-2004 6 SOT23-6L package dimensions change for reference “D” from 3.0 millimeters (0.118 inches) to 3.05 millimeters (0.120 inches). 20-Mar-2008 7 Reformatted to current standard.
PAGE 14
DALC208 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.