Datasheet

DocID14117 Rev 4 11/44
B5973D Functional description
44
The synchronization feature of a set of the B5973D is simply get connecting together their
SYNC pin. The device with highest switching frequency will be the MASTER and it provides
the synchronization signal to the others. Therefore the SYNC is an I/O pin to deliver or
recognize a frequency signal. The synchronization circuitry is powered by the internal
reference (V
REF
) so a small filtering capacitor (100 nF) connected between VREF pin and
the signal ground of the Master device is suggested for its proper operation. However when
a set of synchronized devices populates a board it is not possible to know in advance the
one working as Master, so the filtering capacitor have to be designed for whole set of
devices.
When one or more devices are synchronized to an external signal, its amplitude have to be
in comply with specifications given in Table 4 on page 6. The frequency of the
synchronization signal must be, at a minimum, higher than the maximum guaranteed natural
switching frequency of the device (275 kHz, see Table 4) while the duty cycle of the
synchronization signal can vary from approximately 10% to 90%. The small capacitor under
VREF pin is required for this operation.
Figure 5. Oscillator circuit block diagram
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