Datasheet

DocID022801 Rev 5 25/42
A7986A Application information
The guidelines for positioning the poles and the zeroes and for calculating the component
values can be summarized as follows:
1. Choose a value for R
1
, usually between 1 kΩ and 5 kΩ, in order to have values of C4
and C5 not comparable with parasitic capacitance of the board.
2. Choose a gain (R
4
/R
1
) in order to have the required bandwidth (BW), that means:
Equation 30
where f
ESR
is the ESR zero:
Equation 31
and Vs is the sawtooth amplitude. The voltage feed-forward keeps the ratio Vs/Vin constant.
3. Calculate C
4
by placing the zero one decade below the output filter double pole:
Equation 32
4. Then calculate C
3
in order to place the second pole at four times the system bandwidth
(BW):
Equation 33
For example with V
OUT
= 5 V, V
IN
= 24 V, I
O
= 3 A, L = 18 μH, C
OUT
= 330 μF, and ESR = 35
mΩ, the Type II compensation network is:
In Figure 15, the module and phase of the open loop gain is shown. The bandwidth is about
21 kHz and the phase margin is 45°.
R
4
f
ESR
f
LC
------------


2
BW
f
ESR
----------- -
V
S
V
IN
--------- R
1
⋅⋅⋅=
f
ESR
1
2π ESR C
OUT
⋅⋅
--------------------------------------------=
C
4
10
2π R
4
f
LC
⋅⋅
-------------------------------=
C
5
C
4
2π R
4
C
4
4BW⋅ 1–⋅⋅⋅
--------------------------------------------------------------=
R
1
1.1kΩ= R
2
150Ω= R
4
4.99kΩ= C
4
82nF= C
5
68pF=,, ,,