Datasheet

DocID022801 Rev 5 15/42
A7986A Application information
6 Application information
6.1 Input capacitor selection
The capacitor connected to the input must be capable of supporting the maximum input
operating voltage and the maximum RMS input current required by the device. The input
capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR,
affecting the overall system efficiency.
So the input capacitor must have an RMS current rating higher than the maximum RMS
input current and an ESR value compliant with the expected efficiency.
The maximum RMS input current flowing through the capacitor can be calculated as:
Equation 6
where Io is the maximum DC output current, D is the duty cycle, and η is the efficiency.
Considering η=1, this function has a maximum at D= 0.5 and is equal to Io/2.
In a specific application the range of possible duty cycles must be considered in order to find
out the maximum RMS input current. The maximum and minimum duty cycles can be
calculated as:
Equation 7
and:
Equation 8
where V
F
is the forward voltage on the freewheeling diode and V
SW
is voltage drop across
the internal PDMOS.
The peak-to-peak voltage across the input capacitor can be calculated as:
Equation 9
where ESR is the equivalent series resistance of the capacitor.
Given the physical dimension, ceramic capacitors can well meet the requirements of the
input filter sustaining a higher input RMS current than electrolytic/tantalum types. In this
case the equation of C
IN
as a function of the target V
PP
can be written as follows:
I
RMS
I
O
D
2D
2
⋅
η
---------------–
D
2
η
2
-------+⋅=
D
MAX
V
OUT
V
F
+
V
INMIN
V
SW
–
------------------------------------ -=
D
MIN
V
OUT
V
F
+
V
INMAX
V
SW
–
--------------------------------------=
V
PP
I
O
C
IN
F
SW
⋅
------------------------- 1
D
η
----–


D
D
η
---- 1D–()⋅+⋅ ESR I
O
⋅+⋅=