Datasheet

ManualsBrandsSTMICROELECTRONICS ManualsPMICsPMIC - DC/DC voltage regulator Holder HSOP 8

April 2009 Rev 6 1/41

A5973D

Up to 2 A step down switching regulator

for automotive applications

Features

■ Qualified following the AEC-Q100

requirements (see PPAP for more details)

■ 2 A DC output current

■ Operating input voltage from 4 V to 36 V

■ 3.3 V / (±2 %) reference voltage

■ Output voltage adjustable from 1.235 V to 35 V

■ Low dropout operation: 100 % duty cycle

■ 250 kHz Internally fixed frequency

■ Voltage feedforward

■ Zero load current operation

■ Internal current limiting

■ Inhibit for zero current consumption

■ Synchronization

■ Protection against feedback disconnection

■ Thermal shutdown

Application

■ Dedicated to automotive applications

Description

The A5973D is a step down monolithic power

switching regulator with a minimum switch current

limit of 2.25 A so it is able to deliver up to 2 A DC

current to the load depending on the application

conditions. The output voltage can be set from

1.235 V to 35 V. The high current level is also

achieved thanks to an HSOP8 package with

exposed frame, that allows to reduce the R

th(JA)

down to approximately 40 °C/W. The device uses

an internal p-channel DMOS transistor (with a

typical R

DS(on)

of 250 mΩ) as switching element

to minimize the size of the external components.

An internal oscillator fixes the switching frequency

at 250 kHz. Having a minimum input voltage of

4 V only it fits the automotive applications

requiring the device operation even in cold crank

conditions. Pulse by pulse current limit with the

internal frequency modulation offers an effective

constant current short circuit protection.

HSOP8 - exposed pad

Figure 1. Application schematic

www.st.com

Summary of content (41 pages)

PAGE 1
A5973D Up to 2 A step down switching regulator for automotive applications Features ■ Qualified following the AEC-Q100 requirements (see PPAP for more details) ■ 2 A DC output current ■ Operating input voltage from 4 V to 36 V ■ 3.3 V / (±2 %) reference voltage ■ Output voltage adjustable from 1.
PAGE 2
Contents A5973D Contents 1 2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 Maximum ratings . . .
PAGE 3
A5973D Contents 8.1 Component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.2 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.3 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.4 Short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.5 Application circuit . . . . . . . . . . . . . . .
PAGE 4
A5973D Pin settings 1 Pin settings 1.1 Pin connection Figure 2. 1.2 Pin connection (top view) Pin description Table 1. Pin description N Pin Description 1 OUT 2 SYNCH 3 INH 4 COMP 5 FB 6 VREF 3.3 V VREF. No cap is requested for stability. 7 GND Ground. 8 VCC Unregulated DC input voltage. Regulator output. Master/slave synchronization. A logical signal (active high) disables the device. If INH not used the pin must be grounded.
PAGE 5
A5973D Electrical data 2 Electrical data 2.1 Maximum ratings Table 2. Absolute maximum ratings Symbol Value Unit 40 V V V V8 Input voltage V1 OUT pin DC voltage OUT pin peak voltage at Δt = 0.1 μs -1 to 40 -5 to 40 I1 Maximum output current int. limit. V4, V5 Analog pins 4 V -0.3 to VCC V -0.3 to 4 V 2.25 W Operating junction temperature range -40 to 150 °C Storage temperature range -55 to 150 °C Value Unit 40 (1) °C/W V3 INH V2 SYNCH PTOT TJ TSTG 2.
PAGE 6
A5973D 3 Electrical characteristics Electrical characteristics TJ = -40 °C to 125 °C, VCC = 12 V, unless otherwise specified. Table 4. Electrical characteristics Symbol VCC RDS(on) IL fSW Parameter Operating input voltage range Test condition V0 = 1.235 V; I0 = 2 A Min Max Unit 36 V 0.250 0.5 W 4 MOSFET on resistance Maximum limiting current (1) Typ VCC = 5 V 2.25 3 3.5 VCC = 5 V, TJ = 25 °C 2.5 3 3.5 212 250 280 kHz 100 % 1.
PAGE 7
A5973D Electrical characteristics Table 4. Electrical characteristics (continued) Symbol Parameter Test condition Min Typ Max Unit VREF V 0.74 V 0.25 0.45 mA Synch function High input voltage VCC = 4.4 to 36 V; 2.5 Low input voltage VCC = 4.4 to 36 V; Slave synch current(2) Vsynch = 0.74 V Vsynch = 2.33 V 0.11 0.21 Master output amplitude Isource = 3 mA 2.75 3 V Output pulse width no load, Vsynch = 1.65 V 0.20 0.35 μs Reference voltage IREF = 0 to 5 mA VCC = 4.
PAGE 8
A5973D 4 Datasheet parameters over the temperature range Datasheet parameters over the temperature range The 100% of the population in the production flow is tested at three different ambient temperatures (-40 °C; +25 °C, +125 °C) to guarantee the datasheet parameters inside the junction temperature range (-40 °C; +125 °C). The device operation is so guaranteed when the junction temperature is inside the (-40 °C; +150 °C) temperature range.
PAGE 9
A5973D 5 Functional description Functional description The main internal blocks are shown in the device block diagram in Figure 3. They are: ● A voltage regulator supplying the internal circuitry. From this regulator, a 3.3 V reference voltage is externally available. ● A voltage monitor circuit which checks the input and the internal voltages.
PAGE 10
A5973D 5.2 Functional description Voltages monitor An internal block continuously senses the Vcc, Vref and Vbg. If the voltages go higher than their thresholds, the regulator begins operating. There is also a hysteresis on the VCC (UVLO). Figure 4. 5.3 Internal circuit Oscillator and synchronization Figure 5 shows the block diagram of the oscillator circuit. The clock generator provides the switching frequency of the device, which is internally fixed at 250 kHz.
PAGE 11
A5973D Functional description Figure 5. Oscillator circuit block diagram Figure 6. Synchronization example SYNCH OUT SYNCH OUT A5973D FB A5973D FB COMP COMP SS/INH SS/INH GND GND SYNCH OUT SYNCH OUT A5973D FB A5973D FB COMP SS/INH 5.4 GND COMP SS/INH GND Current protection The A5973D features two types of current limit protection: pulse-by-pulse and frequency foldback. The schematic of the current limitation circuitry for the pulse-by-pulse protection is shown in Figure 7.
PAGE 12
A5973D Functional description threshold. The frequency shifter (Figure 5) functions based on the feedback voltage. As the feedback voltage decreases (due to the reduced duty cycle), the switching frequency decreases also. Figure 7. 5.5 Current limitation circuitry Error amplifier The voltage error amplifier is the core of the loop regulation. It is a transconductance operational amplifier whose non inverting input is connected to the internal voltage reference (1.
PAGE 13
A5973D Functional description In fact, when the current of the power element is equal to the inductor current, the diode turns OFF and the drain of the power is able to go high. But during its recovery time, the diode can be considered a high value capacitor and this produces a very high peak current, responsible for numerous problems: ● Spikes on the device supply voltage that cause oscillations (and thus noise) due to the board parasites.
PAGE 14
A5973D 5.8 Functional description Thermal shutdown The shutdown block generates a signal that turns OFF the power stage if the temperature of the chip goes higher than a fixed internal threshold (150±10 °C). The sensing element of the chip is very close to the PDMOS area, ensuring fast and accurate temperature detection. A hysteresis of approximately 20 °C keeps the device from turning ON and OFF continuously.
PAGE 15
A5973D Additional features and protection 6 Additional features and protection 6.1 Feedback disconnection If the feedback is disconnected, the duty cycle increases towards the maximum allowed value, bringing the output voltage close to the input supply. This condition could destroy the load. To avoid this hazardous condition, the device is turned OFF if the feedback pin is left floating. 6.
PAGE 16
A5973D 7 Closing the loop Closing the loop Figure 9.
PAGE 17
A5973D 7.1 Closing the loop Error amplifier and compensation network The output L-C filter of a step-down converter contributes with 180 degrees phase shift in the control loop. For this reason a compensation network between the COMP pin and GROUND is added. The simplest compensation network together with the equivalent circuit of the error amplifier are shown in Figure 10. RC and CC introduce a pole and a zero in the open loop gain.
PAGE 18
A5973D Closing the loop whereas the zero is defined as: Equation 5 1 F Z1 = -----------------------------------2 • π • Rc • Cc FP1 is the low frequency which sets the bandwidth, while the zero FZ1 is usually put near to the frequency of the double pole of the L-C filter (see below). FP2 is usually at a very high frequency. 7.
PAGE 19
A5973D Closing the loop If the damping coefficient δ is very close to zero, the roots of the equation become a double root whose value is ωn. Similarly for ALC the poles can usually be defined as a double pole whose value is: Equation 11 1 F PLC = --------------------------------------------2 • π • L • C OUT 7.
PAGE 20
A5973D Closing the loop Example: Considering RC = 2.7 kΩ, CC = 22 nF and CP = 220 pF, the poles and zeroes of A0 are: FP1 = 9 Hz FP2 = 256 kHz FZ1 = 2.68 kHz If L = 22 µH, COUT = 100 µF and ESR = 80 mΩ, the poles and zeroes of ALC become: FPLC = 3.39 kHz F0 = 19.89 kHz Finally R1 = 5.6 kΩ and R2 = 3.3 kΩ. The gain and phase bode diagrams are plotted respectively in Figure 11 and Figure 12. Figure 11. Module plot Figure 12. Phase plot The cut-off frequency and the phase margin are: Equation 16 F C = 22.
PAGE 21
A5973D Application information 8 Application information 8.1 Component selection ● Input capacitor The input capacitor must be able to support the maximum input operating voltage and the maximum RMS input current. Since step-down converters draw current from the input in pulses, the input current is squared and the height of each pulse is equal to the output current.
PAGE 22
A5973D Application information Where VF is the freewheeling diode forward voltage and VSW the voltage drop across the internal PDMOS. Considering the range DMIN to DMAX, it is possible to determine the max IRMS going through the input capacitor. Capacitors that can be considered are: Electrolytic capacitors: These are widely used due to their low price and their availability in a wide range of RMS current ratings.
PAGE 23
A5973D Application information Table 7. Output capacitor selection Manufacturer Series Cap value (µF) Rated voltage (V) ESR (mΩ) Sanyo POSCAP(1) TAE 100 to 470 4 to 16 25 to 35 THB/C/E 100 to 470 4 to 16 25 to 55 TPS 100 to 470 4 to 35 50 to 200 KEMET T494/5 100 to 470 4 to 20 30 to 200 Sprague 595D 220 to 390 4 to 20 160 to 650 AVX 1. POSCAP capacitors have some characteristics which are very similar to tantalum.
PAGE 24
A5973D 8.2 Application information Layout considerations The layout of switching DC-DC converters is very important to minimize noise and interference. Power-generating portions of the layout are the main cause of noise and so high switching current loop areas should be kept as small as possible and lead lengths as short as possible. High impedance paths (in particular the feedback connections) are susceptible to interference, so they should be as far as possible from the high current paths.
PAGE 25
A5973D Application information compensate for the losses in the overall application. For this reason, the switching losses related to the RDSON increases compared to an ideal case. ● Switching losses due to turning ON and OFF.
PAGE 26
A5973D Application information RDS(on) has a typical value of 0.25 @ 25 °C and increases up to a maximum value of 0.5. @ 150 °C. We can consider a value of 0.4 Ω. TSW is approximately 70 ns. IQ has a typical value of 2.5 mA @ VIN = 12 V. The overall losses are: Equation 25 2 P TOT = R DSON • ( I OUT ) • D + V IN • I OUT • T SW • F SW + V IN • I Q = 2 = 0.4 • 2 • 0.3 + 12 • 2 • 70 • 10 –9 • 250 • 10 –3 + 12 • 2.5 • 10 –3 ≅ 0.
PAGE 27
A5973D Application information In short-circuit conditions VOUT is negligible so during TOFF the voltage across the inductor is very small as equal to the voltage drop across parasitic components (typically the DCR of the inductor and the VFW of the free wheeling diode) while during TON the voltage applied the inductor is instead maximized as approximately equal to VIN.
PAGE 28
A5973D Application information Figure 16. Short-circuit current VIN = 24 V Figure 17. Short-circuit current VIN = 36 V 8.5 Application circuit Figure 18 shows the evaluation board application circuit, where the input supply voltage, VCC, can range from 4 V to 36 V and the output voltage is adjustable from 1.235 V to 6.3 V due to the voltage rating of the output capacitor,.
PAGE 29
A5973D Application information Figure 18. Evaluation board application circuit Table 9. Component list Reference Part number Description Manufacturer C1 GRM42-2 X7R 475K 50 4.7 µF, 50 V Murata C2 POSCAP 6TAE330ML 330 µF, 6.3 V Sanyo C3 C1206C221J5GAC 47 pF, 5%, 50 V KEMET C4 C1206C223K5RAC 22 nF, 10%, 50 V KEMET R1 5.6 kΩ, 1%, 0.1 W 0603 Neohm R2 3.3 kΩ, 1%, 0.1 W 0603 Neohm R3 22 kΩ, 1%, 0.1 W 0603 Neohm D1 STPS3L40U 2 A, 40 V L1 DO3316T-153MLD 15 µH, 3.
PAGE 30
A5973D Application information Figure 19. PCB layout (component side) Figure 20. PCB layout (bottom side) SL Figure 21.
PAGE 31
A5973D 8.6 Application information Positive buck-boost regulator The device can be used to implement a step-up/down converter with a positive output voltage. The output voltage is given by: Equation 32 D V OUT = V IN ⋅ ------------1–D where the ideal duty cycle D for the buck boost converter is: Equation 33 V OUT D = ----------------------------V IN + V OUT However, due to power losses in the passive elements, the real duty cycle is always higher than this.
PAGE 32
A5973D Application information Figure 22. Positive buck-boost regulator 8.7 Negative buck-boost regulator In Figure 23, the schematic circuit for a standard buck-boost topology is shown. The output voltage is: Equation 37 D V OUT = – V IN ⋅ ------------1–D where the ideal duty cycle D for the buck boost converter is: Equation 38 – V OUT D = ----------------------------V IN – V OUT The considerations given in Section 8.7 for the real duty cycle are still valid here.
PAGE 33
A5973D Application information Figure 23. Negative buck-boost regulator 8.8 Synchronization example See Chapter 5.3 for details. Figure 24. Synchronization example 8.9 Compensation network with MLCC at the output MLCCs (multiple layer ceramic capacitor) with values in the range of 10 µF-22 µF and rated voltages in the range of 10 V-25 V are available today at relatively low cost from many manufacturers.
PAGE 34
A5973D Application information Equation 41 1 - < bandwidth f Z ESR = ----------------------------------------------2 ⋅ π ⋅ ESR ⋅ C OUT f LC < f Z ESR < 10 ⋅ f LC The figure below shows an example of a compensation network stabilizing the system with ceramic capacitors at the output (the optimum component value depends on the application). Figure 25.
PAGE 35
A5973D 8.10 Application information External SOFT_START network At start-up the device can quickly increase the current up to the current limit in order to charge the output capacitor. If soft ramp-up of the output voltage is required, an external soft-start network can be implemented as shown in Figure 26. The capacitor C is charged up to an external reference through R and the BJT clamps the COMP pin. This clamps the duty cycle, limiting the slew rate of the output voltage. Figure 26.
PAGE 36
A5973D 9 Typical characteristics Typical characteristics Figure 27. Line regulator Figure 28. Shutdown current vs junction temperature Figure 29. Output voltage vs junction temperature Figure 30. Switching frequency vs junction temperature Figure 31.
PAGE 37
A5973D Typical characteristics Figure 32. Junction temperature vs output current Figure 33. Junction temperature vs output current Figure 34. Efficiency vs output current Figure 35.
PAGE 38
A5973D 10 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
PAGE 39
A5973D Package mechanical data Table 10. HSOP8 mechanical data mm inch Dim. Min. Typ. A Max. Min. Typ. 1.70 Max. 0.0669 A1 0.00 A2 1.25 b 0.31 0.51 0.0122 0.0201 c 0.17 0.25 0.0067 0.0098 D 4.80 4.90 5.00 0.1890 0.1929 0.1969 D1 3 3.1 3.2 0.118 0.122 0.126 E 5.80 6.00 6.20 0.2283 0.2441 E1 3.80 3.90 4.00 0.1496 0.1575 E2 2.31 2.41 2.51 0.091 e 0.10 0.00 0.0039 0.0492 0.095 0.099 1.27 h 0.25 0.50 0.0098 0.0197 L 0.40 1.27 0.0157 0.
PAGE 40
A5973D 11 Revision history Revision history Table 11.
PAGE 41
A5973D Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.