Data Sheet

6.2.3 Ground plane
Here are some recommendations with respect to the ground plane design:
• Do not route any tracks to the right of the STM32WB5MMG and keep a large ground plane with the
associated ground via.
• Route the tracks down directly on the top layer or with via to the other layers.
• The ground plane must include the presence of vias (distance between two vias = 2 mm).
Figure 6. STM32WB5MMG ground plane layout
Ground via
Ground plane
Tracks
6.2.4 Sensitive GPIOs
This board contains three sensitive GPIOs as defined below:
• PB10
• PB11
• PC5
The GPIO locations are illustrated in Figure 7
When PB10, PB11 and/or PC5 are used, a 3.3 pF capacitor in a small package such as the 0201 or smaller, must
be placed as close as possible to the output pin. Also border the GPIO tracks with the ground plane.
Figure 7. Sensitive GPIO location
Superposition of
four layers
Layer 1
Layer 4
Sensitive GPIO location on layer 1
Sensitive GPIO location on layer 4
6.2.5 Four layer reference board design
The reference schematics are illustrated in Section 6.2.5 and the associated PCB layout is illustrated in
Section 6.2.5
By using all the pads, the mother board must be designed with 4 layers.
STM32WB5MMG
Layout recommendations
DS13252 - Rev 3
page 13/41