Datasheet

SLCFxxxM2TU(I)(-x) CompactFlash Card
Datasheet
61000-07000-106, May 2011 13
Signal Name
Type
Pin
Number
Description
-REG
(PC Card Memory Mode
except UDMA protocol
active)
Attribute Memory Select
-DMACK
(PC Card Memory Mode
when UDMA protocol is
active)
I
44
This signal distinguishes between accesses to Common
Memory (high) and Register Attribute Memory (low). In PC
Card Memory Mode, when UDMA protocol is supported by
host and host has enable UDMA on the card, the host shall
keep the –REG signal negated during the execution of any
DMA Command by the device.
This is a DMA Acknowledge signal that is asserted by the
host in response to (-)DMARQ to initiate DMA transfers. In
TrueIDE Mode, while DMA operations are not active, the card
shall ignore the (-)DMARQ signal, including a floating
condition. If DMA operation is not supported by a TrueIDE
Mode only host, this signal should be driven high or
connected to VCC by the host. A host that does not support
DMA and implements both PC Card and TrueIDE modes of
operation need not alter the PC Card mode connections
while in TrueIDE mode as long as this does not prevent
proper operation all modes
-REG
(PC Card I/O Mode except
UDMA protocol active)
DMACK
(PC Card I/O Mode when
UDMA protocol is active)
The signal must also be active (low) during I/O Cycles when
the I/O address is on the bus. In PC Card I/O Mode, when
UDMA protocol is support by host and host has enable
UDMA on card, the host shall keep the –REG signal asserted
during the execution of any DMA Command by the device.
Same as (-)DMACK above.
-DMACK
(TrueIDE Mode)
Same as (-)DMACK above.
WP
(PC Card Memory Mode)
Write Protect
O
24
The CF Card does not have a write protect switch; therefore,
this signal is held low after the completion of the reset
initialization sequence.
-IOIS16
(PC Card I/O Mode)
A low signal indicates that a 16 bit or odd byte only operation
can be performed at the addressed port.
-IOCS16
(TrueIDE Mode)
In TrueIDE Mode this output signal is asserted low when this
device is expecting a word data transfer cycle.